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LDPC codes iterative decoding algorithm and its hardware implementation

Author: YuXinQiao
Tutor: WangZhongXun
School: Yantai University
Course: Signal and Information Processing
Keywords: LDPC codes Iterative Decoding Soft-decision decoding Hard decision decoding FPGA
CLC: TN911.22
Type: Master's thesis
Year: 2011
Downloads: 41
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Abstract


Low Density Parity Check (Low-Density Parity-Check Codes, LDPC) is proposed by Gallager in 1962 based on sparse check matrix of a linear block code , it caused its excellent performance close to the Shannon limit communication areas of sensation , it is another major leap in the history of error-correcting codes following the Turbo code and the current LDPC codes is very likely to be identified as the fourth-generation mobile communications error correction code encoding scheme , so it has become today 's communications experts and scholars of the research hotspots . Iterative decoding algorithm of this paper, research , impact the validity and reliability of the communication performance of the LDPC codes hard decision algorithm and soft decision algorithm detailed analysis , and to find a suitable hardware implementation of the decoding algorithm algorithm. This article can be broadly divided into two levels: theoretical analysis and hardware design theory research , the paper first introduces the background knowledge of the channel coding and LDPC codes , followed by the basic principles of LDPC codes and common construction method and coding algorithm discussed , the focus LDPC code is based on two major categories of hard decision and soft-decision iterative decoding algorithm , respectively, in both the decoding complexity and error rate of in-depth analysis , the paper describes a method of reducing the number of iterations to improve translation code speed decoding algorithm, which is suitable for the more stringent requirements of real-time systems . Finally, build the AWGN channel simulation platform , the difference in performance of the various algorithms and various set parameters for the decoding performance . By simulation analysis , to find a way to achieve decoding complexity and reliability of a good compromise algorithm , based on this algorithm it hardware design . Hardware design , this paper based on the target FPGA implementation of LDPC code decoder design to Normalized BP-Based decoding algorithm for theoretical support , using Verilog HDL hardware description language , and to take a top-down design methodology of LDPC codes translation codec design, given the overall block diagram of the decoder module implementations as well as decoding function of each module in the Quartus II software environment will be integrated into a complete decoder , and translation transcoder comprehensive compilation the function timing simulation to verify the design of the decoder .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Information Theory > Channel coding theory
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