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Design and implementation of a digital speed radar receiver

Author: ShiDeYou
Tutor: CaiZhengYu
School: Nanjing University of Technology and Engineering
Course: Communication and Information System
Keywords: FPGA SOPC down convete velocity measurement
CLC: TN957.5
Type: Master's thesis
Year: 2012
Downloads: 56
Quote: 0
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Abstract


As the continuous development of large scale integrated circuit,especially the improvement of FPGA technology,it make the electronic system design methodology thinking newer.Recently,one FPGA even integrates center processing unit and digitial signal processing core to codesign hardware software,that provide strong support for realization of system on programmable chip.SOPC technology is proposed as a flexible and cost-effective SOC solution by Altera Corporation.We can customize the processor and peripheral interface according to the requirements and the system has many advantages,such as real-time、cost-effective、small size and so on.This thesis proposed taking use of the SOPC technology, realize the hardware platform of digital receiver system of velocity measurement radar on FPGA. According to the basic principle of velocity measurement radar, design software running on this platform. The whole system has two parts, such as FPGA hardware module and NiosⅡprocessor. As the FPGA hardware module, it mainly researches how to realize digital down converter, digitial filter and FFT. The core section of system is NiosⅡprocessor and it control the operation of the system. NiosⅡprocessor receives the result of FFT and calculates by software, we can get the speed. The peripheral interface of the processor mainly includes SDRAM and UART and so on.After testing, the results show that the system can achieve the purpose of velocity measurement.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radar > Radar equipment,radar > Radar receiving equipment
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