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Hardware Design of ABS-S Digital Satellite Set-topbox Motherboard

Author: DingWei
Tutor: DengMing
School: Chinese Geology University (Beijing)
Course: Communication and Information System
Keywords: ABS-S Digital satellite set - top boxes MPEG-2 AVL1108 SDRAM
CLC: TN948.55
Type: Master's thesis
Year: 2009
Downloads: 110
Quote: 1
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Abstract


June 9, 2008, with the success of the \\reached the international advanced level, is not compatible with the existing foreign satellite transmission standard, plus other technical measures can ensure the safety of the direct broadcast satellite business. China's vast territory, in order to solve the outlying rural and pastoral areas to watch and listen to the difficult problem of broadcast TV, the country started coverage works, by expanding rural radio and television coverage to meet the visual needs of the masses of working people. The ABS-S digital satellite set-top box is a set-top box to support domestic ABS-S digital broadcast satellite television standard, is one of the engineering major technical solution adopted for direct broadcast satellite \In this thesis it is in this context of development in line with the development status of China's satellite digital TV satellite digital TV set-top boxes. ABS-S digital satellite set-top box development projects, responsible for the design and implementation of the ABS-S digital satellite set-top box motherboard hardware. The motherboard Power Logic software schematic design and the Power PCB PCB draw. This motherboard adopts the Conexant digital TV decoder chip CX24146 build system for the core and peripheral circuits, including the high-frequency ABS-S board, SDRAM, FLASH, DAC, UART, etc.. ABS-S HF board is constructed the by Transit Union Division the demodulation chip AVL1108 and the SHARP6303 LNB, satellite signals can be received convert TS stream, through a simple interface to the back-end decoder chip. The set-top box software is stored in flash memory, input is available online via the JTAG port, the simulation program. FLASH used to store system control program AM29LV320DB-90EI. EEPROM using AT24C64A, IIC bus control read and write, for storage channels and program data. MPEG-2 decoder of the external memory shared a SDRAM, the capacity of 64Mbits, used to store intermediate data, i.e., when the program is run data area and a stack. The final completion of the motherboard hardware design and implementation, and the actual simulation and testing, the indicators reached a set-top box required to prove that the realization of the design is simple, stable operation can be used as a set-top box solutions.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > TV > TV and television equipment > Television transmitter and receiver equipment > The receiving device
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