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Design of a Four Stages Pipeline Digital Signal Processing Core

Author: WangShiHu
Tutor: MoTingTing；GaoWei
School: Shanghai Jiaotong University
Course: Software Engineering
Keywords: DSP data path floating-point Two-Path Algorithm Booth algorithm Wallace tree shift register
CLC: TP368.11
Type: Master's thesis
Year: 2008
Downloads: 70
Quote: 1
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Abstract


Digital Signal Processor is widely used in high speed data processing areas. With the development of DSP core porcessing speed, processing precision, programming flexibility and programming facility, especially with the development of semiconductor manufacturing process, various 32-bit floating point DSP processors are designed and manufactured since 1980’s. It is important for us to design the IP core of DSP owing property rights for developing advanced SOC products.In this paper, four stages, 16-bit fix-point digital signal processing core is proposed. And the FPGA and ASIC implementation of the DSP core is proposed.The research work of this paper mainly includes:1、The paper analyzes the addition, subtraction, multiplication, Shifter algorithm of fix-point, researches the flow of Processor, determines the data path structure of the calculation components, the calculation of fix-point mantissa and the fixed-point was done in twos-complement;2、In the paper a fix-point Two-Path addition operation data path was provided based on the improved Two-Path algorithm which was expounded by Quach and the feature of fix-point process;3、A multiplication module is devised on the Radix-4-Booth algorithm and the 4-2 Compression tree, which shares the data path with the 2 CLA addition component of Two-Path addition operation data path, so the area of data path was reduced;4、The data path of fix-point DSP IP core is designed, and addition, multiplication, shift register components are implemented;5、The emulation and verification of the data path was finished.This paper has a significant influence on the design of the fix-point DSP processor, and is also of reference value to the design of the float operation components.

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