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Setup the Verification Environment for HW Cowork with SW Base on SkyEye and Gemini

Author: ZhouQiang
Tutor: GuoZuo；HuJian
School: Shanghai Jiaotong University
Course: Software Engineering
Keywords: Software Co-Work with Hardware Accelerated Verification System Socket Platform
CLC: TN47
Type: Master's thesis
Year: 2009
Downloads: 81
Quote: 0
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Abstract


As soon as the complex SoC design developments, the loading for the verification becomes higher and higher. And the requirement for verification is also include the high quality for the function and code coverage, which is also need high performance for the duration cost under the pressure of time-to-marketing.For the system level function verification, developing with the ESL, more and more method imply base on that, which setup the system level transaction model, and apply the upper driver on that transaction model, which is do benefit for software test, and also be benefit for hardware to estimate the performance of hardware structure. As for now, SkyEye is a template for system development environment base on software, which use software core to take place the hardware design, for the purpose to develop software on the embedded system. And that methodology is very means for verification on system level.As for the hardware verification method, more and more EDA vendor focuses their main energy on verification performance, especial on time cost. The paper noted the tools named Gemini is the present for this field. Gemini has two common user modes, the one is Co-Sim mode, the other is ICE mode. And the good performance on Gemini could lower the simulation time, but also could help verification engineer to find out the bug issue on the accelerated platform. And this platform own high performance base on using simulator alone.The project will create a HW&SW co-operation accelerated verification system. And the advantage for the verification platform includes: by now, there is no user or EDA vendor provide the method for co-work for both the two verification methodology, and the project will research and study the way to connect the two environment to make the co-work idea turn to reality; and which primary control flow deal by ISS of SkyEye, and the purpose of the project is provided a SoC verification method, which help software’s test driver apply on hardware design earlier and provide ASIC hardware debug method apply on that more flexible; finally, this method will use the socket method, which make the test environment and the test driver divided, which could help different test engineer finish their task as their habit, and easy to debug, and more, this method could improve the efficiency of ASIC chip level test, and give higher successful confidence of ASIC tape-out.The meaning of this project is created a new accelerated verification system which hardware Co-Work with software on SoC design, which based on the two absolute systems. The chip verification system could help software and hardware improve each other, and which is a meaning experiment.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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