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Design and Authentication of Ethernet Access Control System

Author: LiuGuangKai
Tutor: LiangManGui
School: Beijing Jiaotong University
Course: Pattern Recognition and Intelligent Systems
Keywords: Ethernet Access Control Collision Generator FPGA Verilog HDL
CLC: TP393.11
Type: Master's thesis
Year: 2009
Downloads: 118
Quote: 4
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Abstract


Ethernet is a communication protocol which is employed the most widely in local area network (LAN). Most methods of access control today are used to prevent illegal IP users from accessing Network outside LAN. However, they can not stop the mutual accessings between host computers inside the LAN that is connected by hub, which will destroy the mechanism of QOS. So the research of access control inside LAN is valuable for securing QoS and safety of network.The existing researches on access control are introduced firstly. Then the protocol of Ethernet, which is followed by a method of access control based on the layer of data link for the purpose of access control inside Ethernet. Then the master plan, including the inner structure of the whole access control system, the module dividing and the design of FPGA is expatiated, especially the most important part of the system called Collision Generator. After that, the detail of each module with testing data results and simulation waveform is given out.In the paper, solutions to the key functional modules of access control system such as Receive module, Transmit module and the interface between MAC and PHY are given based on FPGA and verilog HDL. There exists a key point that how to divide and define each module when designing the system. What also very important is that how to coordinate and interconnect these modules. Method of Top-down is also applied to design. The interface signals between modules are defined to communicate for the interconnection, and the internal timing of the module is controlled by states machine. The implementation of Access control function is designed based on Xilinx’s FPGA in this paper. The key modules are described with Verilog HDL in RTL level. At last, a testbench is written to simulate the modules.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Computer network > Local area network (LAN), metropolitan - area network (MAN) > Ethernet
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