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The Design and Implementation and Research of HDTV Monitor Test Pattern Generator

Author: ZuoShi
Tutor: MaChao
School: East China Normal University
Course: Communication and Information System
Keywords: HDTV test pattern Qt FPGA Avalon interface
CLC: TN949.197
Type: Master's thesis
Year: 2009
Downloads: 70
Quote: 0
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Abstract


The improvement of technology related to digital multimedia has changed our life greatly nowadays. It not only enriches our everyday’s entertainment, but also brings us more vivid audiovisual experiences. According to this demand, HDTV (high definition television), which is propagandized as "to feel like watching the real scene on the spot", appears at people’s living room gradually. But the question is how we can make the best choice among the overwhelming amount of HDTV monitors. Therefore it make sense for us to resolve the problem of easily measuring the high definition quality factors of HDTV monitors or other HD-compatible playback devices. Now that the tranditional methods of mesauring and calibrating TV monitor using test pattern is effective and widely accepted, we implement our test device on a basis of this method. In this paper, we design a HDTV monitor test device based on a series of advanced test patterns.This paper contains three major sections. Firstly we concentrate on the work of collecting, sorting, redesigning and instantiating test patterns adapted to HD devices in accordance with the definitive and systematic rules for selecting HDTV still test pictures to be used for properly assessing high-quality factors. We bring forward 6 catalogs, 35 items and more than one hundred test pictures in all, which include all the patterns recommended by China SJ/T standards. Secondly, we develop a dedicated software to generate all of the test pictures, and every pic can be selected as different resolutions or file types. This application software is constructed by Nokia Qt class-library platform and ".dll" files under windows environment. Last, we design a portable player based on FPGAs from Altera in order to display HD test pictures. We establish the player by using Avalon fabric as the on-chip bus architecture, using Nios processor as the center of management and control and transfering test patterns data to Display Module through DMA to accelerate data rate between Avalon interfaces. Then Display Module will encode the received data according TMDS protocal, and output to DVI peripheral of HDTV. In addition, we also make further discussion about follow-up development and maintainment.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > TV > TV : Press the institutional sub- > Digital TV
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