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Design and Implementation of a High-speed Data Acquisition System Based on PCI Express Bus

Author: MaPing
Tutor: LiXuZhi；TangWeiHua
School: Graduate School, Chinese Academy of Sciences
Course: Applied Computer Technology
Keywords: PCI Express bus PCI-E bus FPGA High - speed data acquisition
CLC: TP274.2
Type: Master's thesis
Year: 2008
Downloads: 649
Quote: 1
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Abstract


With space observation techniques to full-spectrum, high-resolution, the weather direction of development, access to remote sensing data and code rate of increasing. In order to ensure the the aerospace ground application system is capable of real-time processing and display of the remote sensing image data, the need to develop a high-performance data receiving and processing system. Among them, high-speed data acquisition record is one of the key technologies. This thesis is based on serious research in related areas of Research, a third-generation I / O interconnect PCI Express bus to achieve high-speed data acquisition and processing system. And comprehensive consideration of factors such as performance and cost, to determine based a dedicated chip bus protocol PEX8311 to design PCI Express bus interface. The hardware design of the entire high-speed data acquisition and processing system uses a modular design structure, the hardware system is divided into differential data reception, data cache, PCI Express bus interface, as well as local bus control logic, and so the main module. PCI Express bus interface PCB design and local temporal logic is the emphasis and difficulty in the design. The design and development of system software, including device drivers and user applications. Driver development strictly follow the development model of the WDM driver, and use a functional but powerful DriverStudio development environment to complete; application design using the design of multi-threaded architecture and asynchronous I / O operations, not only enhanced with the interaction between the users, but also greatly improved the efficiency of the data processing. In the pre-design of this project, the system design of the high-speed signal integrity analysis and simulation of programmable logic; system later debugging real-time digital oscilloscope and TDR sampling oscilloscope signal quality and impedance of the entire hardware system commissioning validation, and debugging results to evaluate the performance of the system error rate is also discussed in detail the main problems and solutions in the debugging process. The build closed loop transceiver test environment, system functionality and performance testing. Show that the system has been tested in real-time transceiver 320Mbps high-speed data streams, have met the needs of practical application. Meanwhile, in view of the use of FPGAs as a local logic controller, the system has a lot of versatility and flexibility, can be widely used in other high-speed data acquisition, signal processing, and other occasions.

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CLC: > Industrial Technology > Automation technology,computer technology > Automation technology and equipment > Automation systems > Data processing, data processing system > Data collection and processing systems
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