|
With energy-efficient , micro- electronic products , low distortion , high efficiency power amplifier design to become a research focus . Although conventional linear amplifier distortion is small , but the efficiency is not high, but also requires a large area of the heat sink . Class D audio amplifier using CMOS technology with high integration , low power consumption , and occupation of the small size and other characteristics , has been widely used in PDA, cell phone , MP3 player and other portable electronic devices . This paper first introduces the development status of the audio amplifier , classification and works , as well as audio amplifiers some important parameters, then the Class D audio amplifier systems analysis , including Class-D modeling of the feedback loop stability , bridge power driver the structure of the circuit , the output filters of the analysis and efficiency calculation . The detailed description and analysis of the circuit design of each module in the system , and the results of the simulation are given . Then made ??a detailed description of the territory optimization are introduced , the ESD design as well as the snapback principle , listed at the end of the the chips the MPW After the test results . Class D amplifier design operating voltage range from 2.5V to 5.5V , the maximum output power of 2.7W, with fewer external components , without output filter characteristics , better save PCB board space . Main circuit by the op amp input stage, the triangular wave generating circuit , and the PWM modulation module, power module, the power output stage , the overtemperature overcurrent protection modules . Important consideration in the design of the output power , total harmonic distortion and dead time . The layout of the territory , the differential op amp common centroid matching method to reduce the input offset ; land line isolation of sensitive signals between the digital module ; completely separate the left and right channels , reducing crosstalk between channels . The test chip efficiency is 90% , 5V supply voltage , quiescent current less than 5mA current 0.1μA shutdown , power supply rejection ratio 77dB, THD less than 0.15 % , and fully meet the design goals . 0.35μm N - well CMOS process nasty piece success of the current design of the chip in the Semiconductor Manufacturing International ( SMIC ) and succeeded in mass production .
|