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Research on High Performance and Low Power Design of Embedded Memory Management Unit

Author: XuHongMing
Tutor: TanNianXiong
School: Zhejiang University
Course: Circuits and Systems
Keywords: Embedded memory management unit On-chip cache Address Translation Lookaside Buffer Resource reuse Low power consumption Coded locking mechanism Dynamic expansion Multi-process shared Generic coprocessor interface Coprocessor extension
CLC: TP333.1
Type: Master's thesis
Year: 2010
Downloads: 121
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Abstract


With the rising design complexity of embedded applications, storage management has become the focus and difficulty of the embedded system hardware and software design. Virtual storage technology is based on the operating system relative to the transparent approach to storage management software to simplify the application software memory management mode, improve the portability of the program. Integrated in the processor's memory management unit is the basis of virtual storage technology hardware, but the traditional TLB (Translation Look-aside Buffer) design technology hardware costs and power consumption significantly, a major bottleneck for embedded processor design. This paper focuses on high-performance, low-power embedded memory management unit architecture design of key technologies, research and innovations include: a cache-based resources shared TLB design technology. TLB and the on-chip cache has similar storage structures and access patterns, this paper presents a through reuse Cache storage resources of high-performance, low-power TLB design, eliminating the traditional method of the TLB memory hardware resources and static power consumption , reducing the area of ??the core. The method recorded by the establishment of a cache address mapping table, the TLB entry in the cache address mapping, which can effectively reduce the number of visits of the TLB entry in the cache to reduce dynamic power consumption. 2, multi-process TLB entries shared cache line window design method. The cache line is divided into different process window to prevent the process of switching the frequent replacement of the TLB entry. Make full use of the structural characteristics of the cache to achieve the dynamic expansion of the TLB entry, to solve the problem of limited number of the traditional TLB design entries to expand the range of physical memory mapping, improve TLB hit rate. Further proposed a reuse cache replacement policy TLB entry coded lock, maximize ease TLB entry instructions, data resources) and Tunisia. 3, support for multi-page size two TLB low-power architecture. The method is an effective solution to the TLB and the data and instruction accesses the cache resource conflicts, reduce the number of visits of the TLB entry cache. The first level TLB expanded dynamically supports two page sizes, without operating system support, improve the hit rate of the first-level TLB. Experimental results show that, compared with the traditional TLB design, the application of the method of the embedded processor power consumption decreased by 28.11%, 21.58% reduction in area, performance was essentially flat. In this paper, a number of TLB key technologies for embedded processors to improve performance, reduce power consumption, reducing the area has a positive meaning.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory > In the internal memory (main memory ) General
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