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Research and Application of Design for Test in Digitial IC Design

Author: ZhangYan
Tutor: HanYan
School: Zhejiang University
Course: Microelectronics and Solid State Electronics
Keywords: Design for Test Scan Adaptive scan Memory Built-in Self-Test Test
CLC: TN431.2
Type: Master's thesis
Year: 2010
Downloads: 164
Quote: 2
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Abstract

With the application of very deep sub-micron technology, the density of chips increases greatly, but on the other hand it causes the defects during the manufacturing process rising. Therefore, it becomes very important to find a way to detect these defect, design for test (DFT) solves this problem well. The difficulty lies in sequential circuits for DFT, the perfect solution is scan design. With the increase of sequential cells, adaptive scan has gradually been adopted. A large number of various embedded memory are integrated in digital chips, as the constraints of chip ports, direct test of these memories is very difficult. Based on above issues this paper studied in-depth on design for test of digital IC design, and the proposed design method applied in MAC(Media Access Controller) and EPA(Ethernet for Plant Automation) chips.This paper elaborated the approach of scan design flow and adaptive scan flow in sequential circuits. With ensuring the fault coverage, the adaptive scan can be ten-fold reduction in the number of test vectors, thus reducing test time and ultimately reduce the cost of chip. The scan solution was applied to MAC chip design and the adaptive scan was applied to EPAchip design, then we assessed the chip area and vectors loading time.On testing the memories, firstly this paper described in detail on the features of single-port (SP) SRAM (Static Random Access Memory) and dual-port (DP) SRAM, then presented the common functional fault models (FFMs), finally proposed the built-in self-test (BIST) test strategies of the SP SRAM and DP SRAM. The test strategy of word-oriented memory can directly been extended from the bit-oriented memory, the only need is to select the appropriate background data, it has been done in this paper.If you use the ATE (Automatic Test Equipment) to test the scan function of the testability chip sample, the cost is enormous. This paper proposed a test platform for a testability sample and discussed in detail of the test methods for scan function.The test results of the DFT function show that the methods described in this paper were feasible.The innovations in this paper include:1、The features of SP and DP SRAM have been studied and the same as to SP and DP Register file, the test strategies have been proposed for the word-oriented SP and DP SRAM and Register file.2、This paper proposed a highly cost-effective test solution for the chip samples capable of testability function and set up the test platform.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > Semiconductor integrated circuits ( solid state circuits ) > Bipolar > Digital ICs, logic ICs
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