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AFDX end system design based on FPGA
Author: LuoXi
Tutor: HuXiaoLong
School: Central South University
Course: Computer Science and Technology
Keywords: AFDX FPGA End system IP core
CLC: TN915.04
Type: Master's thesis
Year: 2011
Downloads: 112
Quote: 0
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Abstract
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AFDX is a new generation of aircraft avionics messaging system . Based on AFDX standard , built an FPGA-based AFDX end system development platform . In order to simplify the hardware design , AFDX end system development platform using Xilinx Virtex-4 FX12 FPGA as the core SOPC . The FPGA contains a PowerPC 405 processor hard core and two full-duplex Ethernet MAC hard-core . Complete the PowerPC 405 chip calculation function, dual MAC AFDX redundant interconnection . Avionics interface with the the CPCI interface and aviation electronic systems is possible . Taking into account the ease of implementation and flexibility , AFDX protocol AFDX - specific link layer and other layers separated . AFDX link layer part of a self-designed soft IP core to achieve complete integrity check in the receiving process , redundancy management, as well as the sending process flow adjustment , redundancy management and other functions . Taking into account the client system according to actual needs of different scheduling algorithms , in order to facilitate the IP core multiplexed into other design , scheduling module and the IP core design of the separation . The scheduler is implemented in software , scheduling algorithm in the weighted fair queuing algorithm based on the consideration of the frame transmission time , taking into account the priority , the length of the interframe gap , jitter many requirements, scheduling the sending order .
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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication network > General issues > Communication protocols, communication protocols
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