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Research of FPGA Implementation ME/MC Based Frame Rate Up Conversion in HDTV

Author: ChenSunYang
Tutor: ChenYingZuo
School: Shanghai Jiaotong University
Course: Communication and Information System
Keywords: HD TV Motion Estimation Motion compensation Frame rate to enhance VLSI
CLC: TN949.17
Type: Master's thesis
Year: 2010
Downloads: 76
Quote: 1
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Abstract


According to the plan, China 2015 will be shut down analog TV, fully into the era of digital television. LCD panel due to the small size, beautiful appearance, cost advantages to be widely used in the digital TV. With the display size increases, the the inherent blur in the LCD panel (shadow), motion blur (motion blur) phenomenon has become particularly prominent, especially in the performance of fast motion scenes visual effects more serious decline. To solve this problem, some manufacturers from the physical characteristics of the liquid crystal panel, the response time to reduce the liquid crystal molecules of the panel; repeated to improve the screen refresh frequency and some simple frame; also some in the black frame is inserted between the two images, gray frame method to improve the refresh rate. These simple processing method for the enhancement of the visual effect is not obvious. Recent studies focus is mainly based on the motion estimation and motion compensation (Motion Estimation and Motion Compensation, ME / MC) multiplier. Between every two images interpolated by calculation of a virtual image, when a virtual image of this operation out approximation to the \The topics It is in this context, of research motion estimation and frequency with hardware circuit. This paper studies the hardware circuit based the frame interpolation multiplier simulation algorithm, and the algorithm based on the characteristics and requirements of the hardware implementation cropped, to enable it to meet the requirements of real-time processing of the video signal, without reducing the subjective visual effects. The main work of this paper are as follows: (1) improved parity array structure motion estimation Lai et al. Improved motion estimation maintain a high-speed parallel computing characteristics improved, while enabling the working frequency of the circuit; (2) achieve Lai structure and improving the structure of the motion estimator; verify the the parity array motion estimator function and timing; (3) configuration of the multi-port memory controller (MPMC) IP Core, to build a simulation platform to test through multiple ports simultaneously read and write memory; (4) of the video frame is divided into vertical strips with the processing program, to reduce the total number of times of access to the external memory and time; (5) using a multi-level storage cache frame data respectively, the program of the search window data and the macro block of internal data. Hierarchical storage of data, reducing the bandwidth requirements between the ME / MC processing module with external memory; This paper first reviews the basic theory of the ME / MC algorithm and its application in the the interpolation frame octave processing, then elaborated based ME / MC frame interpolation multiplier algorithm steps. Then a whole hardware circuit and multi-level storage structure, the design of the system interface, water treatment, as well as the master state machine. Chapter study the existing architecture of the realization of the full search motion estimation and Lai structure was improved to achieve results. Chapter 5 gives a basic multi-port memory controller integrated with the simulation results, and system debugging platform structures. Chapter VI of the full text of a summary and outlook for future research and development of the subject.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > TV > TV : Press the institutional sub- > High-resolution (high definition ) TV
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