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The Key Technology of Asynchronous Routing Node in Network on Chip

Author: LiXiaoJun
Tutor: YangYinTang
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Network on Chip Routing Virtual channel Arbiter Crossbar
CLC: TN47
Type: Master's thesis
Year: 2010
Downloads: 79
Quote: 1
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Abstract

With the continuous development of nanoscale CMOS integrated circuit technology and system-on-chip technology, chip multiprocessor already beginning to move in the direction of multi-core and isomerization development, and the current system-on-chip designs widely shared bus structure gradually become a constraint multicore processing system performance bottleneck, has been unable to meet the needs of system-on-chip interconnection network for system-on-chip design, in order to solve the problems of communication between the on-chip components, namely, an on-chip network. -Chip network to overcome the shortcomings of poor scalability of the bus structure, provides a viable on-chip communication mechanisms for the billion-transistor era, and has a high reusability communication structures and communication services, including on-chip reusability. For chip network, routing design is the key to performance, but due to the shortcomings of the synchronization circuit in the power consumption and delay, it must adopt a new circuit asynchronous circuits. The paper conducted a systematic study on the the critical asynchronous routing node on-chip network technology. The first introduces route basic asynchronous circuit unit, such as Unit C, Muller pipeline, MUX, etc., and the handshake protocol, the structure and design principles described in detail. Introduction of static virtual channel to effectively solve the problem of routing packets microchip caused connection port competition and lead to the obstruction by the competition, and improve the system throughput, but when more of the input ports, virtual channel will become constrained chip area and one of the main parameters of the power consumption of the system, therefore the papers and from the dynamic point of view to discuss how to effectively allocate virtual channel. Secondly, based on the traditional cross-switch structure, discussed controllable bandwidth, high-speed and low-power cross-switch structure, cross-switch structure based on a variety of queuing mechanism and its scheduling algorithm, a detailed description of the buffered crossbar switch and the local buffer Crossbar The structure and principle of proposed the RR circuit structure, and simulation based on SMIC 0.18μm CMOS process. Finally, a time delay insensitive asynchronous virtual channel arbiter detect virtual priority input channel to choose arbitration priority authorization and order of authorization, to avoid deadlock and congestion, and the threshold of the door use the arbiter delay insensitive, the full asynchronous virtual channel arbiter priority dynamic variable, its advantages of scalability to meet the service needs of the on-chip network.

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