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Clock Duty Cycle Stabilizer on Chip Based on PLL Techniques

Author: XuMing
Tutor: ZhuZhangMing
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Chip clock Duty cycle stabilizer Pipelined A / D converter Delay lock loop BiCMOS
CLC: TN792
Type: Master's thesis
Year: 2010
Downloads: 149
Quote: 0
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Abstract


For the purposes of the pipelined A / D converter , the clock stabilization circuit is a key module circuit . The dynamic performance of the duty cycle of the clock signal deviates from a certain range of 50% will give SNR serious impact , with the system input signal frequency increases , the duty cycle of the clock signal and the jitter performance of the A / D converter the signal-to-noise ratio , the effective number of bits , and clutter - free dynamic range of more and more impressive , so the clock the stability circuit in such systems have a wide range of applications . Delay lock loop DLL synchronization , can produce phase interval such as the characteristics of the multiphase clock signal having the phase of the input and output , and its application in the clock duty cycle stabilization circuit is quite extensive. This paper first introduces the basic principles of analog phase-locked loop design a delay PLL clock duty cycle stabilizer circuit structure . The analysis of the stability of the clock duty cycle of the A / D converter performance , the parameters of the jitter of the clock signal on the constraints of the actual A / D converter up signal - to - noise ratio and effective median , obtained in a given channel noise ratio, the maximum clock jitter formula for clock stability circuit to determine the parameters of jitter performance basis . Each clock stability circuit module circuit designed based ASMC0.35μm 3.3/5.0V BiCMOS process , including analysis and design of high-speed clock buffer circuit , phase detector , charge pump , loop filter , voltage-controlled delay line the multi-phase non-overlapping clock generation circuit analysis and design . On this basis , each module circuit using Cadence Spectre simulation verification , validation, and parametric testing and the overall circuit functional simulation . Simulation results show that the stable clock circuit based on the delay lock loop structure can produce multi-phase non-overlapping clock input clock frequency of 100MHz and 125MHz clock duty cycle can be adjusted to the range of 10% to 90% regulation accuracy is better than 50% 5% , lock time of less than 1μs, and performance to meet the design requirements .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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