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The digital - to - analog converter (DAC) is an important part of the key member of the digital and analog systems interface , but also the signal processing system , has long been widely applied in the field of communications, video and audio, etc. . The continuous development of semiconductor manufacturing technology and devices provided the conditions for the DAC design uses full NMOS device . This thesis is based on the study of the various DAC system structure , working principle and the way , comparison, analysis, design based on the architecture of the TSMC 0.25μm process NMOS 10 1GSample / S DAC and analog core circuit . The segmented current steering DAC form, including digital portion ( register , the decoding circuit, a control circuit, and clock ) , and a simulation portion (the reference voltage source , reference and the reference current source , the current source array , a switch array ) , and on this basis , specify the function of each module and work . The study analyzed the match and limited output impedance of the current source , switch -resistance injection effect , complementary switch off the impact of the performance of the current source array , switch array module design based on TSMC 0.25μm process , the whole the circuit configuration of the current source of the NMOS device , and switch modules , the circuit structure has a high matching , the high output impedance of the current source and a low conduction resistance , non-overlapping clock signal control of the complementary switches . Optimized by numerical calculation and simulation , the device parameters and the module circuit structure , and the circuit structure of the current source and a switch module meet performance indicators determine the segmented coding using 28 of the structure, and based on this structure , there is obtained NMOS 10 1GSample / S DAC analog core circuit structure , application Cadence Hspice software to the simulation , the simulation results : cycle 1ns, the full scale of the output current for 29.975mA, DNL is less than ± 0.5LSB INL less than ± 1LSB, to the design specifications , and laid the theoretical and technical foundation for the further study of the NMOS - wide high-speed high-precision digital-to-analog converter .
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