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IEEE802.16e standard LDPC decoder, FPGA Design and Implementation

Author: YangJianPing
Tutor: ChenQingChun
School: Southwest Jiaotong University
Course: Communication and Information System
Keywords: IEEE 802.16e LDPC decoder, Offset Min-Sum Algorithm FPGA
CLC: TN911.22
Type: Master's thesis
Year: 2010
Downloads: 345
Quote: 5
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Abstract


LDPC codes comfortable nineties was rediscovered , with its close to the Shannon limit error correction performance, and low decoding complexity , the advantages of high throughput attracted attention , becoming the Turbo code after channel coding profession another research focus. Today , LDPC codes have been widely used in DVB-S2, CMMB and communications systems such as Wi-Fi , IEEE 802.16e standard was adopted as an optional channel coding scheme . With the further deepening of theoretical research , LDPC code is also very likely in the future fourth generation mobile communication system has been applied . This article is based on the IEEE 802.16e standard , discussed the standard LDPC code decoder FPGA design and implementation issues. This paper analyzes and compares the LDPC codes several soft-decision decoding algorithm for error correction performance and decoding complexity, selected to achieve excellent performance and low complexity Offset Min-Sum algorithm for this article decoder decoding hardware implementation algorithms, and identified through software emulation offset Min-Sum algorithm shift factor β value of 0.125 , fixed-point format ( 6:3 ) . And the analysis and comparison of existing LDPC code decoder based on the structure , suitable for a selected structural features quasi- cyclic LDPC decoder as part of the parallel structure to achieve this basic structure of the decoder , and to improve and the decoded is not only to support the IEEE 802.16e standard rate in all six and 19 yards long LDPC code decoding , but also has a continuous block of data processing functions and dynamic stop decoding iteration functions. After re- built decoder based ModelSim functional simulation test platform for the various functions of the decoder for validation testing and using Quartus Ⅱ in Stratix Ⅱ GX series FPGA devices decoder on a comprehensive optimization . Consolidated results showed that: the decoder operating frequency of 150MHz , the fixed 15 iterations , the minimum can reach 95Mbps decoding throughput, fully meet the requirements of the IEEE 802.16e standard . Finally, the paper realized the same with the other decoder implemented using FPGA IEEE 802.16e standard LDPC code decoder were compared. Comparison results show that this decoder implemented relatively more resources for the occupancy conditions, more than any other decoder versatility and practicality , and has higher throughput and greater improvement.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Information Theory > Channel coding theory
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