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A 12-bit 1GHz Current-Steering D/A Converter IP Core

Author: WangFengJuan
Tutor: YangYinTang
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: High-speed D / A converter Current Steering Cascode High-speed clock CMOS
CLC: TN47
Type: Master's thesis
Year: 2010
Downloads: 45
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Abstract


In this thesis, using SMIC 0.18μm mixed signal CMOS technology to design a 12 - bit segmented current steering structure D / A converter IP core . 534 segmented , high - five and the middle three thermometer code weighted current source structure , control column decoder and row decoder on a unit current source matrix ; Low four binary weighted current sources . The focus of this thesis was studied the clock circuit module, and the voltage - current conversion circuit module . The clock is part of a distributed clock , drive capability , high accuracy , and the structure is simple and easy to implement ; voltage - current conversion circuit using wide swing cascode structure and provide a precise constant current source for the D / A converter . Cadence environment using Spectre Verilog-A simulation and Matlab tools on the SUN workstation and microcomputer design and simulation . In load 50Ω condition , the output voltage swing of ± 1V, the full-scale current of 20mA , integral nonlinearity error of less than ± 0.26LSB differential nonlinearity error of less than ± 0.4LSB settling time of 1.145ns SFDR of for 89.65dB _AT_ Fclk = 500MHz and Fin = 240MHz , 76.62dB @ Fclk = 1GHz and Fin = 480MHz . D / A converter total system power consumption is 89.1mW @ Fclk = 500MHz and Fin = 240MHz the 97.2mW , @ Fclk = 1GHz and Fin = 480MHz . The effective chip area of ??0.84mm × 1.08mm.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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