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Design and Implementation of ADM in SDH

Author: DengXiaoFei
Tutor: LiHuiJun
School: Shandong University
Course: Communication and Information System
Keywords: Synchronous Digital Hierarchy ADM The E1/VC-4 multiplexer system STM-1/TU-12 demultiplexer system Timing simulation FPGA ISE
CLC: TN914.332
Type: Master's thesis
Year: 2008
Downloads: 221
Quote: 2
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Abstract


At present, most of the countries in the world SDH as the communication backbone network, China's main network basic SDH network. SDH equipment requirements, protocols and more complex structure, SDH-specific integrated circuit design has become an inevitable SDH equipment generally using a dedicated chip to achieve. Add / drop multiplexer ADM SDH network using a network for SDH transmission network at the transit site. Its synchronous multiplexing and digital cross-connect function integrated in one, with a flexible ability to drop any tributary signals, has great flexibility in network design. However, the domestic manufacturers ADM device core chip is mainly dependent on imports, design and development of ADM core chip is imperative. This paper first introduces ADM SDH knowledge and technology, and then gives SDH Add / Drop Multiplexer ADM overall design. The design choices 2Mbit / s to 155Mbit / s multiplex route to design to upload, download E1 signal STM-1 points add / drop multiplexer. The ADM system the E1/STM-1 multiplexer system, demultiplexer system STM-1/E1, digital cross-connect system of three main parts, including its former two most central and important. This paper gives the first two designs, and as a key to the Design and Implementation to select E1/VC-4 Multiplexer and STM-1/TU-12 of demultiplexer. The system uses a top-down design methodology, independent complete RTL-level Verilog HDL coding. Software environment: the Xilinx campus plan ISE 9.1i (genuine), Synopsys company the VCS platform (workstation). The first to use VCS to do functional simulation; subsequently the code file to the ISE environment, Xilinx Spartan 3E XC3S500E-4FG320C (main chip) FPGA configuration options, the completion of the comprehensive use Synplify Pro 8.1; followed to complete the conversion and mapping, layout wiring (to achieve three steps); and then timing simulation, Post-Translate Simulation Post-Map Simulation, Post-Route Simulation three steps; Finally, the use of FPGA hardware board devices to download and give verification, validation results meet the design requirements. This design in strict accordance with the recommendations of the ITU-T standards and national standards; E1/VC-4 multiplexer system and STM-1/TU-12 of the demultiplexer system specific circuit implementation, the source code by independent author write. Final design to be validated by FPGA, the means of verification of functional simulation and timing simulation.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication systems ( transmission system) > Digital communication system > Digital multiplex > Synchronous Digital Hierarchy (SDH)
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