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FPGA-based design and implementation of wireless channel emulator

Author: LiYouXing
Tutor: ZhouXianMin
School: University of Electronic Science and Technology
Course: Signal and Information Processing
Keywords: Radio channel FPGA Rayleigh fading Channel Emulator
CLC: TN791
Type: Master's thesis
Year: 2008
Downloads: 308
Quote: 1
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Abstract


With demand for wireless communications and quality requirements are high, the development of wireless communication devices are becoming increasingly complex, system test equipment development process throughout the proportion is growing. To be able to shorten the development cycle, testers need to simulate in the laboratory the various propagation characteristics of the radio channel to the design of systems for debugging and testing. Radio channel emulator for wireless communication system hardware debugging and testing indispensable instruments. This design is based on a radio channel emulator Clarke channel model as a reference, Jakes model based on improved algorithm, using Altera's Stratix Ⅱ EP2S180 simulation to achieve a frequency selective fading channel. Channel emulator implements four antenna uplink reception of data, each antenna can be distinguished by the eight paths, each path can be distinguished by the reflector 64, with each antenna reflector can distinguish the number of paths and can be configured independently. Each reflector through the initial angle and initial phase setting, and to ensure the angle of the reflector and the phases are uniformly distributed random number, can be made with a reflective path between the non-correlation characteristics in multi-path propagation channel is a discrete sense stationary uncorrelated scattering model (WSSUS). Radio channel emulator simulates the uplink data transmission environment, upstream data generated by the background and stored in single-board SDRAM. Start testing, uplink data under the control of the CPU emulator through the channel, and then served on board baseband demodulation, the final test data bit error rate and block error rate, so as to analyze the uplink receiving performance. First, we study 3GPP TS 25.141 protocol testing requirements for communications equipment and radio channels of their own characteristics, completed the wireless channel emulator absorption system design and modification. Secondly, the structure for the FPGA internal resources to study the channel emulator FPGA implementation process of the difficulties and resource consumption, carried out module division. Completed a major delay module, Rayleigh fading module, backplane interface module into the RTL code development, simulation, synthesis and on-board debugging; complete FPGA and background software co-debugging; finish line for two days to four antennas revision work, so that the internal FPGA operating frequency doubled, dramatically reducing the consumption of FPGA resources. Finally, the completion of the radio channel emulator hardware design, the test of the radio channel emulator protocol according to 3GPP TS 25.141 V6.13.0 the requirements, that is the data block error rate (BLER) in certain circumstances, for different channel propagation environments and under different SNR transmission services (E b / N 0 ) for testing, single-antenna and multi-antenna test results meet the protocol specified in the signal to noise ratio (E b / N 0 ) requirements.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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