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The Research and Design of a High Speed Column Parallel ADC for CMOS Image Sensor System

Author: LiXiaoChen
Tutor: LiBinQiao
School: Tianjin University
Course: Microelectronics and Solid State Electronics
Keywords: CMOS image sensor Column-parallel structure Monoclinic analog-to-digital converter Cyclic analog-to-digital converter
CLC: TN792
Type: Master's thesis
Year: 2007
Downloads: 227
Quote: 1
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Abstract


In today's era of information explosion, the desire of people to information anytime, anywhere. With the continuous advancement of science and technology, portable digital products, with its small size, low power consumption, easy to carry, etc. have a current and future broad market. In the field of video technology, CMOS image sensors for its low power consumption, small size of the camera system, the signal processing circuit and pixel the acquisition array integrated in a chip finest advantages, is gradually becoming a conventional CCD image sensor alternatives. The future development direction of the CMOS image sensor is a large dynamic range, high resolution, high sensitivity, miniaturization and multi-functional. This CMOS image sensor system design put forward higher requirements, With the continuous improvement of the level of technology, the ever-shrinking size, analog circuit design challenges facing growing. Analog-to-digital converter is the interface to the analog world and the digital world is an important part of the analog circuit design. Therefore it is particularly important to find suitable analog-to-digital converter in the CMOS image sensor system. Departure from the demand for CMOS image sensor system for analog-to-digital converter, and discusses the characteristics of the column parallel processing structure of the analog-to-digital converter and applications, and design methods. Taking into account the advantage of the the columns parallel processing structure in data processing speed, accuracy and data throughput of the analog-to-digital converter to become a major design considerations. This paper introduced two rows parallel structure of the analog-to-digital converter: Single-slope ADC and Cyclic ADC systematically expounded the key issues in the two ADC design. To do a more detailed discussion of implementations and design methods of the functional structure of the Single-slope ADC ramp generator, comparator offset, filter selection and readout circuit; theoretical description for Cyclic ADC structure selection the circuit implementations do a more detailed description, especially a CMOS image sensor the important noise - column FPN elimination method, largely to reduce the the column FPN noise on the image quality of the serious interference, has a relatively good The actual effect. The design is based on the foundation of a 0.18um process, is verified by simulation. Single-slope ADC 50MS / s data throughput, 10-bit high-precision and low power consumption of only 10mW. Cyclic ADC to achieve the same 10-bit accuracy requirements, and Single-slope ADC has been greatly improved in the speed ratio, and only needs to complete AD conversion 2us time, such that the frame rate of the image sensor is almost Single-slope ADC structure of the image sensor 6 times, while only consumes about the power consumption of 0.5mW, may be created to further improve performance of the image sensor. Short two kinds of ADC, each has its own characteristics and application environments, two column-parallel analog-to-digital converter.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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