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DBF baseband data Simulator Design and Development

Author: WangXiangRong
Tutor: ShengWeiXing
School: Nanjing University of Technology and Engineering
Course: Communication and Information System
Keywords: radar simulator fiber finite state machine DDS
CLC: TN955
Type: Master's thesis
Year: 2011
Downloads: 31
Quote: 4
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Abstract


During the course of developing digital beam forming (DBF) processor of digital array radar, the performance of DBF processor need to be tested with different targets and interferers. It is very difficult to test the performance and function of DBF processor in perfect true environment. So it is necessary to develop a radar simulator to generate simulated base-band echo signals from all patches of DBF receive array. A large number of array patches and complicated, changing targets set a higher demand on the bandwidth, flexibility, and data real-time to radar simulator.This paper has carried out researches of digital array radar basedata simulator and a fiber interface based simulator proposal is come up with under this background. Spacial location and other characteriscitcs of targets and interferers can be set in the personal computer (PC) and the phase parameters of different patches can be transmitted through USB interface. The simulated basedata can be generated by radar simulator using Direct Digital Synthesizer (DDS) according to the Pulse Repetition Interval (PRI) and then transmited to DBF processor. The hadware designing of primary and secondary configuration based DBF basedata simulator has been completed in this paper, including FPGA peripheral circuit, DDRII memory circuit, Ethernet interface circuit, fiber module circuit, clock generator circuit and so on. The designing of PCB board is done according to the high speed signal integrity criteria and the hardware installation and debugging are also completed afterward. The primary and secondary configuration based DBF basedata simulator consists of two boards:the primary signal processing board and the secondary fiber module interface. These two boards are connected by two FMC interferces which is used to reduce the developing period and makes the simulator become more universal.Some work of PC and FPGA programming are also done after completing the hardware designing, including the basedata generating module, the fiber interface module, USB interface module and PC interface programming and so on. The whole system debugging is done between the simulator and DBF processor and the function of simulator is verified in several experiments. There are many significant features in this simulator, such as huge data interaction bandwidth, far transmission distance, low BER (bit error rate) and so on. Various kinds of targets’and interferers’echoes can be simulated according to the environment.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radar > Radar system simulation
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