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The Schedule Design and System Test of AFDX Switching Chip

Author: ChaiMing
Tutor: QiuZhiLiang
School: Xi'an University of Electronic Science and Technology
Course: Communication and Information System
Keywords: Avionics Full Duplex Ethernet Virtual Link Quality of Service Deterministic
CLC: TP29-AD
Type: Master's thesis
Year: 2008
Downloads: 206
Quote: 3
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Abstract


With the development of avionics electronic systems, moving and sharing information between systems increase requirements of real-time and reliability. The common used avionics bus technology such as ARINC429 can not meet the needs. Based on IEEE 802.3 Ethernet technology, the next generation avionics bus technology standard ARINC664 has presented a new deterministic network suitable for avionics electronic system: AFDX- Avionics Full Duplex Ethernet.Combining with features of avionics bus communication, a new concept called Virtual Link (VL) is introduced in the AFDX network. Each VL configured by system integrator has the deterministic Quality of Service (QoS), so the whole network has the deterministic feature.With the project of“design and implement of AFDX switching chip”, the architecture of AFDX network and principle of the chip are analyzed, the whole design scheme is presented in the dissertation. The simulation and implementation of schedule module described by Verilog HDL is also finished. In the end, a testing scheme special for the chip is given. The actual hardware testing results have shown that design of the chip accords with the ARINC664 standard. The chip operates stably and efficiently.

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