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Research and Application of I~3O Buffering and Scheduling Model in Network Processing

Author: ZhangZuo
Tutor: SunZhiGang
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: Packet Reassemble Scheduling Buffer Queue
CLC: TP393.02
Type: Master's thesis
Year: 2008
Downloads: 2
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Abstract


The rapid development of Internet makes higher demands of network performance. Network nodes enhance the performance of data process as well as provide a certain degree of quality of service control to meet the different applications on different quality of service requirements.Packet buffering and scheduling is an important means that realizes bandwidth and latency control in network nodes.There are a large number of research results on buffer scheduling and service quality assurance of network node.And they have been widely used in the design of network node.I~3O(Interleaved In and Integrated Out) is a common buffer model in the network process, especially the various fragmentation reassembly issues,such as ATM PDU reassembly,IP fragmentation reassembly involve I~3O buffering and scheduling problem.This paper does research on I~3O model,proposes combination I~3O model(CI~3O:Combined I~3O) for the efficient implementation of I~3O model and elaborates buffer requirement,scheduling mechanism and the ability of service quality assurance of CI~3O model.Main research and innovation are as follows.First of all,this paper elaborates the problem of fragmentation reassembly in the network process,abstracts into a unified I~3O model and extracts the key parameters and establishes a good foundation for the research on fragmentation reassembly’s buffering and scheduling issues in the network process.Meanwhile,about sending and receiving path’s shared buffer issues,we introduce CI~3O framework to establish a foundation for study on competition and arbitration brought by shared buffer issue.The second,we study CI~3O framework deeply,propose static management methods of fragmentation reassembly’s buffers.This method support that sending path’s fragmentation buffers share physical memory with receiving path’s fragmentation reassembly buffers,so it has to achieve higher efficiency.In response to the buffer management features,we propose sequential,layered and polling scheduling algorithm.This algorithm reduces the complexity and provides better QoS performance.And it’s suitable for all kinds of application in the network process involved fragmentation reassembly.The third,We do research on the realization of CI~3O framework and its scheduling algorithm.Based on CI~3O static buffer and continuous polling scheduling algorithm,We achieved at receiving and transmitting tablets data at each E1 interface of a 16-way E1 line card, which is been used in the high-performance NGN routers.All buffer management and scheduling by the FPGA,the design has been completed,the 16-way E1 interface line cards in the actual environment has been applied to achieve the desired results. From modeling analysis,algorithms researching and designing we systematically studied buffering and scheduling used in packet reassembly.Our work is of not only of theoretical value, but also a major guiding role in network nodes design and achievement.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Computer network > General issues > Computer network architecture and design
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