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Optimized Design of the High Performance Floating-Point Multiply-Add-Fused Unit

Author: ZhangJingBo
Tutor: XingZuoCheng
School: National University of Defense Science and Technology
Course: Electronic Science and Technology
Keywords: Floating-point multiply-add units Semi-custom design optimization Full-custom design optimization Optimize the design process
CLC: TP332.2
Type: Master's thesis
Year: 2007
Downloads: 74
Quote: 1
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Abstract


The floating-point multiply-add components (MAF) is one of the components of high-performance microprocessor core computing , its speed and power consumption has a great impact on the entire microprocessor performance . Study of semi-custom / full-custom the mixed design optimization to achieve high-performance floating-point multiply-add components with a wide range of application value and practical significance . X microprocessor floating point multiply-add components to study and optimize the design of low latency to support double-precision floating-point multiply-add structure based on using a combination of methods of semi-custom design optimization and full-custom design optimization , in design and optimization algorithm , coding , logic implementation structure , circuit layout levels , significantly enhance the performance of the floating-point multiply-add components . 0.13μm CMOS process , logic synthesis and layout simulation results show that the optimized floating-point multiply-add units operating frequency up to 1GHz, to the optimized design of the target . The results of this research include the following points : 1 . Analysis to study low-latency floating-point multiply-add components based on proposed full floating-point multiply-add components optimized design and optimize the design process summarized a floating-point multiply-add components . Improved addend on order shift calculation and processing order shifter implementation structure , development order shift amount with maximum parallelism of the order shifter so addend on order shift logic operation delay is reduced by 15% . 3 of the ten stops pipelined floating - point multiply-add components , so that the proportion of moderate to optimize the design of full-custom design , to ensure the feasibility of the design optimization objectives . Logically divided in a logical progression , and fine-tune stations logic delay to balancing stations , floating-point multiply-add components to achieve optimal performance . Floating - point multiply-add components optimize the key sub- module of the full-custom design . Full-custom design to achieve high-performance the 4-2 compressor standard cell , 52 or doors and AND gate 108 . ,4- 2 compression maximum delay in the worst conditions of 317ps and maximum delay of 52 -bit or doors 147ps , 193ps maximum delay of 108 bit and doors . Optimize the design of full-custom design module used in the floating-point multiply-add components to achieve a better optimization results .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU) > Arithmetic unit
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