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Research and Realization of the 128-bit Floating-Point Multiply-Add Fused Unit

Author: ZhangFeng
Tutor: XuZuoZuoï¼›LiTieJun
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: Floating-point multiply-add fusion Block multiplication Leading a prediction Priority encoding tree Test set
CLC: TP332.2
Type: Master's thesis
Year: 2007
Downloads: 70
Quote: 1
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Fusion MAF (Floating-Point Multiply-Add Fused) floating-point multiply-add floating-point multiplication and addition is seen as an integral operation , the intermediate result is not rounded to improve the accuracy and throughput of the floating-point calculations . The high-precision floating-point multiply-add integration has become the focus of research with independent intellectual property rights of high-precision floating-point multiply-add integration of components has important significance in promoting the study of China 's high-performance processor . This article studies the architecture and the design method of the multiply-add floating-point integration of components , designed and implemented a 128-bit high - precision floating-point multiply-add components , the main work and results include: 1 . Proposed a 128-bit floating point fusion multiply-add architecture . 5 stops flowing structure ; using block multiplication and addition , to ensure that the floating-point multiply-add operations throughput and reduce the length of the critical path , and improve computing speed ; improved 4:2 binary storage part of the sum-of- adder CSA (Carry SaveAdder) tree structure , reducing the logical progression of the CSA tree structure . 2 . 128 three input leading predictive architecture was designed and implemented . Compares the two input DT leading forecasts and input leading to prediction algorithm , provides a theoretical basis for architecture exploration ; modular priority coding tree , three input leading predictive architecture , leading than traditional two input DT To reduce the forecast area approximately 31% of the critical path delay reduced by 26% . 3 Fusion 128 -bit floating point multiply-add test set generation method . According to the IEEE-754 \\ 854 standard , in accordance with the data calculated characteristics of the input test stimulus data is divided into nine equivalence class targeted artificial selection , as well as randomly generated input stimulus data assurance testing coverage , reduce test vectors , accelerate the validation speed . Based on the test set , 128-bit floating-point integration of components multiply-add logic simulation and FPGA emulation . On 128 floating - point arithmetic unit design using Verilog language synthesizable RTL level code using Design Compiler logic synthesis under in smic0.13 micron process , the frequency up to 202MHz , the critical path delay 4.93ns area of ??approximately 119,000 door.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU) > Arithmetic unit
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