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The Design and Implementation of High-Reliable 8051 and Reliability Estimation

Author: LaiZuo
Tutor: WangSuFeng
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: Highly reliable microprocessor Single-particle events Reliability Enhancement Technology Fault injection
CLC: TP368.1
Type: Master's thesis
Year: 2008
Downloads: 127
Quote: 2
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The past 20 years, with the extensive use of computer technology, many applications require the computer must be long-term, stable and reliable operation, and therefore to receive widespread attention as the reliability of the computer system core microprocessor. Radiation and electromagnetic interference is caused microprocessor main reason for the failure, caused by single-particle effects microprocessor reliability is the focus of the current highly reliable microprocessor design technology research areas. The phenomenon of single-particle effects in single-event upset (SEU) will not damage the logic circuit, but can change the state of the logic circuit signal, resulting circuit disorder that caused the breakdown. SEU has a chance, sudden and randomness, and thus become the main object of protection in the design of highly reliable microprocessor resistance to Single Event Effects. Single event upset (SEU) will cause the microprocessor functional unit failure, will lead to different processor failure. The different functional units of the microprocessor its working mechanism is not the same, and therefore have different reliability enhancement techniques are enhanced reliability. First, the paper analyzes the effect of the single-particle environment, the generation mechanism. Then discusses the effect of the single-particle microprocessor, especially for sequential circuits and combinational circuit. Register in the microprocessor by a single event upset (SEU) events prone to failure, triple modular redundancy technique is its reinforcement. The traditional triple modular redundancy register will be sampled at the same time the fault value resulting in register malfunction. This article will be enhanced spatial and temporal triple modular redundancy for reliability enhancements to the register, and thus improve the reliability of sequential circuits at the same time enhance the performance of fault-tolerant combinational circuit. Enhanced spatial and temporal triple modular redundancy combined temporal redundancy and spatial redundancy, for non-feedback circuit reliability enhancements double edge triggered on the basis of the ordinary space-time triple modular redundancy technology combined with reinforcement feedback circuit register improved. Microprocessor ALU operations unit increase in HR8051 the Berger code detection its computing process monitoring. Berger code detector utilizes the arithmetic function mapping the relationship between computing process to detect the error. For memory and register file, error detection and correction EDAC error detection and correction of their reading and writing process. Control flow detection and scene preservation and restoration of the reliability enhancement implementation for the control unit. The security state machine is used to a state machine controlled by calculation the MDU reliability enhancement. Achieve reliability is enhanced on the basis of the microprocessor HR8051 fault injection to analyze the effect of their behavior under fault conditions for the existence and reliability enhancement technology. Fault injection results show that the space-time triple modular redundancy fault duration is not greater than the clock phase difference of the three cases, shielding combinational logic and clock lines of single event upset (SEU) events. The results show that the increase in the three clock skew can increase the effect of the space-time triple modular redundancy, but the best value. Subsequent the reliability enhancement downward trend; make two clocks at the same time when the fault duration greater than three clock skew sampling to the fault value will lead to a long period of fault status feedback circuit. Finally SystemVerilog assertions mechanisms used in fault testing, combined with fault injection to enhance the technical reliability of the circuit from the system-level test reliability. Concrete realization of the Markov analysis methods combined with the results of fault injection and HR8051, HR8051 behavior in the event of attack of the single-particle turn (SEU), some assumptions and simplifications to analyze the behavior of hot backup system reliability.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Micro-computer > A variety of micro-computer > Microprocessor
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