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Design of Interface with FIFO Features to Control DDR/DDR2 SDRAM

Author: LiYuan
Tutor: MaBoYuan
School: Xi'an University of Electronic Science and Technology
Course: Control Theory and Control Engineering
Keywords: DDR SDRAM FPGA FIFO
CLC: TP333.1
Type: Master's thesis
Year: 2009
Downloads: 674
Quote: 6
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Abstract


In order to meet the need for large-capacity , high-speed storage medium of modern electronics field , DDR SDRAM storage media need better interface control module and more convenient to use . The module system constructed in this paper is the use of an effective means of , and has been applied to multiple transport ZTE North Institute class project . This paper first introduces the background, research status and papers Introduction followed the principle of DDR SDRAM storage devices and the development process , and describes the DDR SDRAM interface timing analysis system function and role , based on the design of program planning . After emphatically describes Stratix-II GX series FPGA DDR2 interface FIFO - based engineering design for the master core unit , the data input unit and data cache unit separate modular analysis , functional simulation and the main modules summarized problems. Then use the chipscope software platform for online debugging , analyze problems and propose related key technical issues and solutions . Through the development and debugging of the system module implements a FIFO storage media interface device characteristics , the convenience of the large capacity of the complex timing interface , the application of high-speed storage medium .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory > In the internal memory (main memory ) General
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