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DSP-based embedded video compression hardware platform design and implementation

Author: YiZhiHua
Tutor: HuFangMing
School: Xi'an University of Electronic Science and Technology
Course: Biomedical Engineering
Keywords: Embedded Video Compression Ping-pong caching DSP FPGA
CLC: TN919.81
Type: Master's thesis
Year: 2007
Downloads: 160
Quote: 1
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Abstract


In some occasions, digital video monitoring through PSTN or GPRS wireless network, users hope to transmit video encoding data, it needs to be highly effective low bit rate video compression algorithm to compress video images. This paper designs and realizes a low bit rate video compression based on DSP hardware platform. Paper first according to the characteristics of the video ADC chip SAA7111 output signal, we design a can guarantee the integrity of the image frame table tennis frame cache used to cache image data acquisition and, and the table frame cache implemented with VHDL language, and has carried on the function of the simulation. Function simulation proves that the ping-pong cache can be a good frame buffer of image data. Then, the paper mainly introduces the hardware design of a DSP processor, DSP minimum system, on how to design how to SDRAM, FLASH external memory expansion, and how to design other on-chip peripherals etc are introduced in detail. Paper has several problems on high speed DSP circuit board design are summarized. The end of the paper, simple introduces DSP integrated development environment CCS2.0 features, and presents a part of the program design idea.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Image communication, multimedia communication > Image coding
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