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The FPGA Design of AES Processor on the IC Card

Author: DengRong
Tutor: ZhangHongNan
School: Hunan University
Course: Microelectronics and Solid State Electronics
Keywords: Advanced Encryption Standard Algorithms Resource Sharing Hardware description language FPGA
CLC: TN409
Type: Master's thesis
Year: 2005
Downloads: 249
Quote: 2
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Abstract


As China's \security protection measures must be sufficient to ensure information security. But now the IC card for multiple DES or T-DES to encrypt and decrypt the encryption algorithm has already been broken. In 2002 the United States announced a new encryption standard - Advanced Encryption Standard (AES), and used for communications and networking, with the Advanced Encryption Standard to ensure information security imperative IC card, IC card for AES coprocessor design is very important. This paper introduces the overall structure of the Advanced Encryption Standard and four round function, and gave details of its encryption / decryption principles and processes. Advanced Encryption Standard hardware implementation of a variety of structures, this thesis compares the pipeline structure, the internal structure of pipeline structure and the speed loop unrolling and features of the IC card information processing for the characteristics and requirements of the area, chose the internal pipeline structure as the IC card structure of the AES coprocessor, and the structure is improved. The key expansion, using a synchronous extension approach that each round operation during the next round of generated while the key, the key scheduling round operation and simultaneously, saving the storage space of the round key. On this basis and on the Advanced Encryption Standard four round function of the algorithm optimized to encrypt and decrypt shared hardware resources. The improved structure is characterized by the maximum extent possible to achieve resource sharing, reducing hardware resource utilization. Based on the hardware design, the paper follows a top-down design approach, the use of coding style can be integrated in the integrated development software ISE6.1 AES coprocessor to complete the various functional modules to write Verilog HDL code, and Third-party software called the ISE Modelsim simulation to verify the correctness of the design, and Xilinx's Virtex series xcv-pq240 based FPGA as the carrier successfully completed the mapping from then integrated into the layout of the whole process, the design The maximum clock frequency of 20.032MHz, the encryption of a data packet rate of 64Mbits / s, encryption speed of 43Mbits / s. The results show that the design meets the timing requirements, to meet the IC card for encryption and decryption coprocessor requirements.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Application
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