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Research on Key Technology of Accelerating Cone-beam CT Reconstruction Based on FPGA

Author: DengJingFei
Tutor: LiJianXin
School: PLA Information Engineering University
Course: Detection Technology and Automation
Keywords: Cone-beam CT Parallel computing FPGA Three - dimensional image reconstruction Reconstruction of accelerated FDK SART Assembly line
CLC: TP391.41
Type: Master's thesis
Year: 2010
Downloads: 41
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Abstract


Computed Tomography (Computed Tomography, CT) technology used in industrial non-destructive testing and medical diagnostics has been to improve the spatial resolution and imaging speed has been a goal of their research and development direction. Cone-beam CT (Cone-beam CT) with isotropic, high spatial resolution data acquisition time is less significant advantages, has become the mainstream of the next-generation CT. But the three-dimensional image reconstruction of massive data simultaneously high-performance computing has become a bottleneck affecting the overall index of cone-beam CT system, limiting the development of cone-beam CT. Three-dimensional cone-beam CT image reconstruction acceleration technology has become one of the focus in the CT field. With the development of the semiconductor manufacturing process, reconfigurable hardware into the field of high performance computing. Field-programmable gate array (Field Programmable Gate Array, FPGA) is executed in parallel on the airspace as a reconfigurable hardware in the time domain has developed rapidly in recent years and has been widely used as a high-performance parallel computing acceleration parts. In this paper, the mainstream of the three-dimensional cone-beam CT reconstruction algorithm, combined with the latest FPGA hardware structures to accelerate the study of the three-dimensional image reconstruction. The main findings are: for massive data processing large-scale data can not be stored in the FPGA internal problems, put forward a data block solving strategies. The steps of the policy data prefetching, and the design of the \time. Design a three-dimensional image reconstruction algorithm in FPGA-based CT parsing class parallel computing architecture. The architecture is based on the the parsing class classical algorithm - FDK parallel computer tablets decomposition, parallel pipelined design ideas. Especially in the most time-consuming back-projection unit, designed to solve assembly line \4 interpolation data, without waiting for the pipeline. The experimental results show that, the architecture higher speedup can be obtained, and has the characteristics of the resource optimization. 3. FPGA implementation for the simultaneous algebraic reconstruction image reconstruction iterative algorithm (Simultaneous Algebraic Reconstruction Technique, SART) will appear storage capacity overload problem, a method to reduce the storage requirements of algorithm. The rearrangement by data the effective reconstruction slice data reorganization within the FPGA only for slicing calculated, and slice iteration. The analysis results show that the method in the reconstruction the XC5VLX330 models FPGA slice size is 512 × 512. 4. Designed a the SART algorithm floating point FPGA-based computing architecture. The architecture is based the SART algorithm operator tablets decomposition, through combination of flowing water on the the each count intergranular order and correlation analysis, using floating-point arithmetic. The experimental results show that, to obtain a higher acceleration than the schema, and has higher achieve accuracy. 5 on the basis of the above study, the design of a new high-performance FPGA-based three-dimensional CT image reconstruction prototype. The program combines FDK count tablets attribute analysis and experimental results verify from the hard core of dynamically reconfigurable multiprocessor heterogeneous and multi-FPGA parallel processing 4 gives the specific design of the program.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices > Image recognition device
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