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Signal Process Hardware Testing Platform Design & Implementation

Author: ZuoXiaoHui
Tutor: TianJinWen
School: Huazhong University of Science and Technology
Course: Pattern Recognition and Intelligent Systems
Keywords: Test Equipment USB2.0 Cache FPGA LVDS
CLC: V443.5
Type: Master's thesis
Year: 2005
Downloads: 198
Quote: 1
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Abstract


In satellite remote sensing devices, with the development of remote sensing technology and the continuous improvement of the transmission observation satellite remote sensing image quality requirements of aerospace remote sensing image resolution and sampling rate is getting higher and higher, the resulting high-resolution remote sensing image data storage capacity and the sharp increase of the amount of transmission data. Must be addressed in order to try to keep the information of high-resolution remote sensing image, enter the contradiction between the data rate and transmission channel bandwidth. Spaceborne high-resolution remote sensing image data of high-fidelity, real-time, large compression ratio compression technology to resolve this contradiction became the key technology. The system with the spaceborne video compression prototype debugging, analog satellite images of the sending end and the receiving end, the establishment of the simulation test platform. In the current application in the background, you can not directly access to remote sensing image video stream. Priori remote sensing image data, the test platform LVDS video signal is generated, the data source to the device under test. In target identification system during the test, the test platform priori target video clips into a video stream, provides an ideal data source for the system under test. In the more general case, the test platform will be pre-generated data is sent in accordance with the provisions of the interface rate. The test platform is also to be completed by the signal acquisition process, replace the corresponding transmitter with the receiver on the hardware connection. Research project named according to the project application background information processing system hardware test platform. The device is divided into core and option modules. The core module with widths up to 16 configurable digital interface, 16MB cache, USB2.0 interface. Optional modules depending on the type of application, complete conversion of the digital signal and other types of signal. Testing platform system by configuring the FPGA IP core to achieve the different characteristics of the digital interface, such as: I2C interface, high-speed synchronous / asynchronous interface with optional modules, digital signal, the analog signal, LVDS signal interface . To achieve 500Mbps high-speed LVDS remote sensing image data rate prescribed interface to send and receive through the USB2.0 interface, with large-capacity high-speed buffer board, asynchronous data sending and receiving process. This paper analyzes the core module implementation technologies such as USB interface technology, the realization of high-speed buffer and signal integrity issues. And then asked the two specific implementations, a single FPGA programs and FPGA DSP program, and analyze the characteristics of the two programs. We chose a single FPGA solutions with the synchronous LVDS digital interface prototype test platform. The article also gives the implementation of two optional modules expand the application.

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CLC: > Aviation, aerospace > Aerospace ( Astronauts ) > Space instrument,spacecraft devices,spacecraft guidance and control > Electronic equipment > Spacecraft remote sensing
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