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Design and Implementation of Co-Designed Dynamic Binary Translation System

Author: XuFan
Tutor: WangZhiYing
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: Prototype system Hardware and software co-design Dynamic Binary Translation Microprocessor
CLC: TP391.2
Type: Master's thesis
Year: 2010
Downloads: 26
Quote: 0
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Abstract


Dynamic binary translation technology was initially used to solve the problem of binary code compatible between different processor platforms, after being applied to the virtual machine design, the virtual machine and an important support technology to enhance the performance of the virtual machine. Dynamic binary translation technology in different sizes such as desktop, server, embedded system virtualization play an important role, to be successfully used, including power management, system security, software cache management instruction set translation, and memory management a number of aspects. However, traditional software-based dynamic binary translation system overhead, code cache management and low efficiency inherent defects. In addition, the multi-core era is a new challenge to the existing dynamic binary translation technology. How to take advantage of the dynamic binary translation and optimization technology to give full play to the advantages of multi-core also become a new topic in front of designers. Soft and collaborative dynamic binary translation system can effectively overcome the inherent defects of the software dynamic binary translation technology, it to customized dedicated hardware module to complete the look-up table, cache management, and other common functions, thereby improving overall system performance. Based on extensive depth study of the current dynamic binary translation and optimization technology development status, explore and propose a method of dynamic binary translation system to achieve in heterogeneous multicore platform hardware and software co. The main research results obtained by this paper are: 1) a heterogeneous dual-core hardware and software collaborative dynamic binary translation system model CDBTS. It execution module on the target processor core, while the translation module on the coprocessor module tailored, and set up a dedicated hardware logic of the look-up table, cache management, improve system performance, but also enhance the The flexibility of the system. 2) designed and implemented a page fault based dynamic binary translation of the VMM. Can capture the missing pages in the user program execution interrupt a smaller overhead monitoring execution of the user program, on the the untranslated code of capture and forwarding the translated code links, etc., and can be easily ported to different target platforms, greatly improving the flexibility CDBTS. 3) customized for CDBTS a dual-port RAM-based code cache, greatly reducing the conflict of the two processors the nuclear access code Cache, ensure the consistency of the data. The Code Cache management strategies and the corresponding hardware management module. 4) analysis of the strengths and weaknesses of the existing dynamic binary optimization systems, combined with the characteristics of multi-core platform, multithreaded dynamic optimization framework for multi-core platform and in-depth study of the use of existing technology to achieve the dynamic optimization framework feasibility, and in CDBTS model of the framework. In order to verify the correctness and validity of the above work, this project is designed to achieve a source architecture IA-32, the target architecture is ARM's software and hardware the collaborative dynamic binary translation the system CDBTS-X2A. The actual test results show that the correct, CDBTS-X2A working outperforms traditional software dynamic binary translation system.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Translator
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