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The Front-end Design and Verification of Scaler Chip for Flat Panel Display

Author: LiShiJie
Tutor: ZouXueCheng；LiuZhengLin
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Scaler Flat panel displays Front-end design Logic verification Image scaling
CLC: TN873
Type: Master's thesis
Year: 2005
Downloads: 130
Quote: 1
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Abstract


This paper presents a method for the the scaler chip front - end design of the flat panel display (Flat Panel Display) , and chip front-end design FPGA implementation on the basis of the logic of functional verification . This paper first introduces the features and scaler works , and then given the structural design of the scaler chip , to finally be on the the scaler chip front-end logic validation process described below , including the proposed verification program , designed to test PCB and verify the results feedback to adjust the design . Designed scaler chip in addition to having the basic functions of the scaling of the input video signal resolution , the back - end processing module through the built-in image enhancement can also output the image effect enhancement processing. The scaler chip body image scaling engine, which is responsible for the image data to the interpolation operation, to change the resolution of the image . Image scaling engine uses bilinear interpolation (Bilinear interpolation) algorithm . In order to reduce the hardware complexity , narrow area , the algorithm of hardware implementation using look-up table method for interpolation coefficients . Scaling engine for the transmission characteristics of the video image , the image of this article separately from the structure of a horizontal direction and a vertical direction scaling . Such a configuration can simplify the complexity of addressing the data portion , and to save circuit area . In addition to these two modules, the scaler chip also includes an input module, display timing control module , the microprocessor interface module auxiliary module . The scaler chip front - end design FPGA logic verification . The actual operating frequency has a certain degree of complexity requiring high scaler chip logic verification , the entire logic verification environment structures need to consider many issues . The focus of this article is the the scaler chip logic verification . The scaler chip front-end design with Verilog HDL language gives the register transfer level (RTL) description and the logic functional simulation . The FPGA platform logic verification results show that the chip front-end design to meet expected performance requirements .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > Terminal equipment > Display device,the display
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