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Research and Hardware Design on Sorting Algorithm of Complex Signal

Author: ZhangGuoQiang
Tutor: ZuoLiPeng
School: Harbin Engineering University
Course: Communication and Information System
Keywords: Signal sorting Sequence difference histogram method FPGA DSP
CLC: TN957.51
Type: Master's thesis
Year: 2010
Downloads: 110
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Abstract


With the development of radar technology , the diversification of the radar system , the complicated and comprehensive utilization of various institutional , electronic countermeasures, electromagnetic environment facing increasingly complex . The radar signal sorting become one of the key technologies of the field of electronic warfare . Only correctly identify the target radar type to enemy radar interference . With the development of modern electronic technology , more and more programmable devices (Field Programmable Gate Array-FPGA) applied to the actual performance of the digital signal processor (Digital Signal Processor-DSP) is rising , This paper describes a DSP-ADSP-TS201 , and the FPGA-Virtex4 build hardware platform , the co-processing of the radar signal separation circuit . The first radar signal processing with a brief introduction , and then details several common radar signal sorting algorithms , and these algorithms do a comparative analysis . Combined with their respective advantages and disadvantages of several algorithms , selected SDIF algorithm as the design of the main sorting algorithms . Finally, according to the actual situation of the hardware platform design and algorithm , a complete set of design options . The main content of the work is as follows : 1, to build the hardware platform, including the system power supply , DSP, FPGA, the dual-port RAM , an external memory configuration circuitry , and necessary peripheral circuits, etc. . Write VHDL, FPGA internal logic function modules , within the sampling time , the completion of the pulse width of the radar signal to reach the pre - sorting of the acquisition time and other parameters . 3 , the preparation of the corresponding sorting algorithm in the DSP program . The FPGA data after the pretreatment is fed to the dual-port RAM , the DSP reads data from the dual port RAM , the use of the sorting algorithm for the corresponding data processing completion signal cobbing work . Practice has proved that the separation of this signal processing board to complete more than one variety of radar signal sorting , have a strong ability to identify sorting .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radar > Radar equipment,radar > Radar receiving equipment > Radar signal detection and processing
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