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BERT （Bit Error Rate Tester） is an essential testing device in communication system during performance testing and malfunction diagnosis the network conditions. The traditional design about BERT are based on CPLD and CPU works together, the disadvantages of traditional design are complicate structure, cost much and hard to taken. With the development of EDA technology nowadays, more and more functions will be integrated on one chip by hardware engineer. The paper analyzed the design requirement of BERT based on FPGA, and made a scheme that use FPGA as the main chip in the system, the structure of the board is star-type, paper bring forward integrated both control and diagnosis function module on FPGA, improved the system’s integration and extend ability, and all the function modules can be designed and modified in RTL level.Paper researched the work theory and structure of traditional BERT, and use VHDL program language to realize a majority of BERT functions on FPGA, such as LCD driver, rs232 driver, error bit test, key and led control, etc.There are mainly 2 part designs in this paper, hardware design and software design which based on FPGA. The hardware design is mainly about the circuits around FPGA, RS232 circuits, E2PROM circuits, key and led layout designs. Software design are mainly about use VHDL programming language to realized some functions like 8 level speed control during 1 to 24MHz, 3 code type to choose -29-1,215-1,223-1, sent error code manually, bit error rate test and some other resources control around FPGA, etc.The design mainly focus on a single FPGA chip, it contains many functions, integrated generate, receive, statistic and calculates the test code, save the result, LCM driver and rs232 communication functions as a whole. With a little exterior assistant circuit can made the whole BERT system, so the size, weight and cost of BERT can cut a lot.The design use menu mode as intuitionist LCD display format, it’s easy to be understood by user, and all controls are based on 4 keys. Compare with the traditional BERT, has the advantages like simple panel, easy to operate, frankly display and easy to update the whole system.Paper finished the BERT demo system at last, including the BERT demo board ver 1.0 and the BERT core based on FPGA ver 1.0, could do some BERT basic functions. The whole hardware cost was cheap, it proved that the BERT system design based on FPGA is effective and reliable.
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