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Passivation layer on the power device chip electrical parameters affect the simulation analysis and process optimization

Author: WangXiaoFeng
Tutor: LiuYang；HuZe
School: University of Electronic Science and Technology
Course: Software Engineering
Keywords: Passivation BVceo negative resistance Small current amplification factor
CLC: TN386.1
Type: Master's thesis
Year: 2010
Downloads: 75
Quote: 0
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Abstract


Passivation is a focus on the means to improve the performance of power devices and improve reliability essential silicon process in high-voltage integrated circuits and power integrated circuits in MOS technology based passivation importance of the more prominent . In the manufacturing process of a bipolar power transistor using LPCVD depositing semi-insulating polysilicon (SIPOS) passivation process can effectively improve the device leakage current characteristics , and improving the device stability . But in practice , is directly deposited in the active region of semi-insulating polysilicon small current of the device has a significant effect of magnification and BVceo characteristics . After routine tests such as high temperature storage devices small current magnification will average about 30% smaller , even up to 50 % a 20% reduction in the average value of K , has seriously affected the performance of the product ; while composite film SIPOS SiO_xN_y improve current magnification devices BVceo negative resistance phenomenon is very serious , low yield . This article by adjusting the passivation layer structure in order to solve the above problems , combined with the actual device can use conditions , two new process is determined by experiments : First, the EB junction passivation layer on the nitride is deposited by PECVD instead of the original silicon SIPOS of TEOS , the actual production by dry etching section instead of the original wet etching , eliminating the hazards of the film undercut ; boron diffusion growth of the oxide layer is retained , eliminating the intermediate process to introduce ion contamination possible, the cleanliness of the oxide layer itself is also guaranteed. The test chip of the two processes , in the test are not BVceo negative resistance phenomenon , and encapsulated die After 168 hours of high-temperature storage test , small current changes mean magnification can be controlled at less than 6% , the K value is the average the rate of change of less than 3% , achieved a significant improvement of the parameters of the chip . Second trial process has been partially applied to the actual production of the current test model extended to another 2-3 chip models ; send customers to trial new technology products , customer recognition .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Semiconductor technology > Field-effect devices > Metal - oxide - semiconductor (MOS) devices
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