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Research of High-Performance Router Structure in Network on Chip

Author: ZhangLiPeng
Tutor: WangChangShan
School: Xi'an University of Electronic Science and Technology
Course: Computer Software and Theory
Keywords: Network-on-Chip Router architecture Crossbar Buffer Energy efficient
CLC: TN47
Type: Master's thesis
Year: 2009
Downloads: 53
Quote: 0
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Abstract


With the growing number of Intellectual Property cores, some problems in bus based System on Chip (SoC) restrict the development of chip size and performance. The problems include limited throughput, power, area, synchronization and system scalability. In order to solve these problems, several research groups propose a new architecture called Network-on-Chip (NoC).As the communication nodes of interconnection network for receiving and transmitting data, the router is the key component of the Network-on-Chip. The performance of the interconnection network mostly depends on the fabric of network routers. In this paper our research is mainly about the design of NoC router in the range of two-dimensional regular framework. The main work of the paper is as follows:The first contribution is the design of a kind of novel modular wormhole-switched router architecture, called Po-Ne. The Po-Ne divides the Network traffic into two distinct and independent modules, Positive module and Negative module. The two modules are completely independent and symmetrical, either one has the independent arbitration and logic. Compared with the existing designs, the Po-Ne which employs path-sets and uses smaller crossbars reduces the output port contention probabilities deeply. And the Po-Ne has a certain degree functionality of fault tolerance.The second contribution is the design of the high-performance router structure, called B-G. B-G employs flexible buffer schema and simple Bus fabric. Although the SoC structure based on bus has been gradually replaced by network-based structure. As the bus is simple and effective, there is still a lot of application space. The origin of the router is central buffer organization, but the shortcoming is no guarantee of bandwidth and latency. However, the smaller and more virtual channels can lead to poor flexibility and utilization of buffer. B-G dynamically establishes multi-FIFO queues in a single buffer, which increase the flexibility of the buffer allocation and utilization; fix the bus architecture to connect the input ports and output ports, which can ease the network congestion and meet some QoS requirement.At last, the Po-Ne and B-G are simulated on OPNET. Simulations show that performance of presented routers is better than the typical structure.

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