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Study and Design of Arithmetic Encoder for JPEG2000

Author: LiuQiWei
Tutor: JinWenGuang
School: Zhejiang University
Course: Circuits and Systems
Keywords: Binary Arithmetic Coding JPEG2000 MQ-coder VLSI
CLC: TN761
Type: Master's thesis
Year: 2006
Downloads: 241
Quote: 2
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Abstract


With the rapid development of computer and digital communication technologies , the communication bandwidth and capacity is limited, the encoding and compression of images and video to become a research hotspot . Arithmetic encoding as an entropy encoding method , having excellent coding performance , its average code length can be in any case , the approximation of the entropy of the source . Therefore, the study of arithmetic coding more and more attention , and has been included in the international standards of many images and videos . JPEG2000 is the Joint Photographic Experts Group in December 2000 by a new generation of still image compression standard . It not only provides beyond the JPEG compression performance , but also provides a rich set of features to meet the growing demand for image coding techniques . It uses the context - adaptive binary arithmetic coding for entropy encoding operation , the MQ encoder is specific forms of implementation of the arithmetic coding . In-depth study of the principles of arithmetic coding , explores the multiplier binary coded form , conditions exchange mechanisms and adaptive probability estimates and other important concepts . MQ coding in the three-stage pipeline processing 1-bit sign is given a one clock cycle based on the structure analysis the MQ coding key operator details and optimization algorithms, in order to achieve higher throughput requirements , this paper discusses the concurrent coding of two symbols , the difficulties in the design analysis and propose solutions strategy , and ultimately the two symbols of a four -stage pipeline concurrent encoding architecture . In this paper, the Verilog hardware description language register transfer level description of the proposed structure , and complete functional simulation, simulation results are given . Performance comparison analysis showed that the first structure operating frequency is 200MHz, consumes 7486 logic gates ; This paper presents two symbols of concurrent coding structure , the operating frequency of 143MHz , consumes 12,547 logic gates that can meet the requirements of high-throughput , the matching parallel structure in one second can handle about 47 × 10 6 gray image pixels , the better the bit-plane coding .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Modulation technique and the modulator,demodulator and the demodulator > Modulation technique and the modulator
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