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With the development of information technology , digital signal acquisition and processing to be more widely used in scientific research , industrial production, aerospace , medical and health departments , these applications of digital signal transmission speed relatively high demand . Based on the ISA bus signal transmission efficiency is low , seriously restricting the improvement of system performance . PCI bus with its high-performance , low-cost , open , software compatibility , and many other advantages to become the most popular computer local bus . However, due to the PCI bus hardware interface is complex and difficult to access , protocol specification cumbersome and other shortcomings , often require a dedicated interface chip as a bridge , in order to solve the issue of this series , we proposed a FPGA-based PCI bus interface bridge logic realization of the program to support PCI burst access mode , a burst length of 8-128 pairs of word length , core FPGA chip ALTERA's Cyclone FPGA series EP1C6Q240C8 capacity of 6,000 logic macrocells , speed -8 , the compiler the system speeds up to 80MHz, and achieved good results . FPGA-based PCI bus interface bridge logic core PCI interface module . PCI interface module in terms of hardware , especially the five functional modules of the address conversion module, data buffer module , external interface module and SRAM DMA control module design and hardware implementation method , analyzed the PCI interface module data transfer way , the use of modular design of the internal control logic and the timing simulation and logic verification , hardware needs software with in order to achieve its function , the design of the device driver is an important part of the thesis Windows XP WDM driver mode composition of architecture , some of the key technology in the device driver development tools and development of systems hardware device drivers . Finally, use the key technologies based on the the FPGA PCI bus interface bridge logic , the PCI data acquisition card , the overall design of the program . The system uses Altera's Cyclone II FPGA family .
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