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System Design and Key IC Implementation of UHF ASK Receiver

Author: WuYueZuo
Tutor: LaiZongSheng
School: East China Normal University
Course: Microelectronics and Solid State Electronics
Keywords: RF receiver UHF ASK RF front-end
CLC: TN85
Type: Master's thesis
Year: 2008
Downloads: 219
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Abstract

Work in the ultra-high frequency (UHF) radio frequency receiver, can be used in intelligent systems, including the field of home security systems, automation and control systems, vehicle access control systems and RF ID, there is a broad market prospect. Because no such chip is reported that foreign chip also multi BiCMOS process, therefore designed to meet the performance requirements of a low-power, low-cost, highly integrated CMOS UHF receiver greater practical significance. Start from the communication standard, system-level design methodology UHF receiver system analysis, design and research. Using the ADS, APPCAD well GENSYS software system parameters, system link budget and validation of simulation. TSMC's 0.18um 2P6M RF / Mixed-Signal CMOS process the key module circuit design and simulation, and layout design. In full on the basis of literature research, this article has achieved the following results: 1) In accordance with the agreement of the European ETSI-300 220 and U.S. FCC protocol PART 15 part of the requirements, the use of the the Okumura model channel analysis is proposed based on the the ASK demodulator way low-IF receiver structure and its frequency program. Link budget target allocation system, and system simulation. 2) for mobile devices, the demand of low-power, index allocation algorithm to minimize the power consumption of a system. , ^{The definition V _IP3i ^{2 / (?) _Ni 2 equivalent dynamic range of the circuit, through mathematical analysis a positive correlation between the equivalent dynamic range and power consumption, and derived indicators can minimize power consumption distribution formula, applied to the design of the RF front-end. 3) design source level coupled common-source common-gate structure low noise amplifier simulation results of its noise figure of 1.2dB, a power gain of 16dB, Ⅱ P3-9.8dBm. Design of active double-balanced Gilbert-type structure mixer, increase the source-level feedback resistor load and low-pass filter to improve the system linear. Simulation results 6.5dB of conversion gain, noise figure of 12.8dB, Ⅱ P3-6dBm. 4) 5 limiting amplifier structure, design logarithmic amplifier with a the RSSI current indication function, a maximum gain of 80dB ASK demodulator. 5) is adopted for the input signal for an improved structure of the pre-amplification, and is designed with a high sensitivity of the peak detector; designed folded common source common-gate structure of the hysteresis comparator, the rise time of the simulation results for 2.3us, when Iref 10uA-3mA range, the delay time of the output waveform of the change in the 3us-120ns. 6) of the circuit layout, including system layout, the key module design, and layout verification parameters extracted. Taken into account in the design of the current density problems, parasitic problems, the symmetry of the problem, the antenna effect, ESD protection.}}

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