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Research on Floorplan in VL SI Physical Design

Author: ChangBaoFang
Tutor: LiLian
School: Lanzhou University
Course: Applied Mathematics
Keywords: VLSI Physical design floorplanning flat hierarchical/multilevel
CLC: TN402
Type: PhD thesis
Year: 2011
Downloads: 173
Quote: 0
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Abstract


Floorplanning is a very crucial step in modern VLSI designs. It dominates the top-level spatial structure of a chip and initially optimizes the interconnections. Thus a good floorplan solution among circuit modules definitely has a positive impact on the place-ment, routing and even manufacturing. In this paper, we propose an efficient approach for the evaluation of the insertion points. The proposed method evaluates In insertion points, instead of all (n+1)2 insertion points as did in the state-of-the-art. The proposed techniques can be integrated into the general simulated annealing algorithm, resulting in a fast algorithm for floorplanning. Experimental results show that, the state-of-the-art can be improved up to 37% in terms of running time, without loss of success rate. In addition, our algorithm is comparable to the state-of-the-art in terms of wirelength.Multilevel strategy is one of the most popular methods for fixed outline floorplan-ning. It partitions an original circuit into some sub-circuits and then merges them into relatively big ones. In this paper, we propose a novel evaluation approach and integrate it into the simulated annealing framework in the merging stage. Moreover, a novel search technique, which can almost keep away from the local optimal, is proposed to obtain bet-ter floorplans. Experimental results show that our approach can obtain better performance than the state-of-the-art in terms of runtime, wirelength and success rate.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design
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