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Research on Wear Leveling Strategy of Satellite Multi-Chip Flash Memory

Author: DaiZuo
Tutor: HuangDeCai；GongWeiHua
School: Zhejiang University of Technology
Course: Applied Computer Technology
Keywords: NAND flash memory large-scale storage embedded file system hot data identification wear leveling
CLC: TP333
Type: Master's thesis
Year: 2011
Downloads: 33
Quote: 0
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Abstract

Currently, more and more space-faring nations tend to use NAND flash memory as the spatial data recorder memory unit, because of its small size, light weight, no moving parts and high reliability. Typically, a flash divided into blocks, each block divided into several pages. Block is the smallest unit of erase operation, and page is the smallest unit of write operation. To rewrite the page, you must perform erase operation on the block where the page in. The number of times each block erase is limited, usually about 1 million times, if a block erase beyond the limit, there have bad blocks, if there are a number of bad blocks in the flash it was broken. The service time of the satellite in space is longer than the general. Therefore, the design of an efficient equalization of wear-leveling to extend the service life of flash memory and to improve the reliability of data storage is great importance for data storage technology of satellites.A good wear-leveling average erase operation to each block as much as possible, and in the process to avoid additional erased. Erase is an additional cause of frequently updated data (hot data) and not the updated data (cold data) stored in one block. The erase unit must be in blocks. When recovering the hot data dirty pages, inevitably cold data pages in the same block should be erased also. So, wear-leveling policy process is generally composed of two parts: (1) to identify hot and cold data. Let the similar "temperature" data pages as much as possible to be stored in one block, to reduce the number of extra erase. (2) As much as possible to store cold data in the larger erase block, to store the hot data in fewer erase blocks, in order to keep balance.By way of analysis and research on existing wear-leveling Algorithm at home and abroad, we found that the current existing algorithms focus on point 2 of the study, while the relative neglect identify hot and cold data pages. Identify hot and cold data in blocks, block erase times is more that consider the hot data stored inside the block, otherwise data that are cold. Identify hot and cold data in this way may have many additional erased, and the existing research has focused on balanced on the wear of monolithic memory, ignoring the characteristics that multi-chip flash memory in wear-leveling can read and write Synchronously. This article on the problems of these studies, combined with multi-chip flash memory can be operated in parallel, we proposed a new recognition algorithm of hot and cold data in order to reduce additional erased. And on the basis of this recognition algorithm, to achieve the complete process of wear-leveling, the simulation results show that the new algorithm has good effect and performance.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
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