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Research on Wideband Digital Receiver and System Implementation

Author: WangHong
Tutor: WangXueGang
School: University of Electronic Science and Technology
Course: Signal and Information Processing
Keywords: Digital receiver Digital down converter Time-interleaved sample Channelized receiver Dynamic range Sensibility Automatic gain control Coordinate Rotation Digital Computer
CLC: TN851
Type: PhD thesis
Year: 2007
Downloads: 2691
Quote: 28
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Abstract


With the fast development of digital techniques, wideband receivers are possible to realized full digitally. Comparing with analog counterparts, digital receivers are of better resolution, reliability, anti-jamming and agility. High dynamic range and sensibility digital receivers are widely used in communication, digital array radar, SAR and high probability intercept, etc. The digital receivers are also crucial for soft-defined radio, where A/D and D/A converters are closer to antenna, and following high speed digital signals are processed on general hardware or software. So studying wideband digital receivers with good performances is very important to adapt modem complicate electromagnetism environment.Wideband digital receivers generally sample analog signals at intermediate or radio frequency. The sample periods may be less than 1ns. It is a challenge for latter digital processing and whole system control. Furthermore, performances of wideband receivers are degraded since they are exposed to more interference than narrow band receivers. This dissertation is focus on important techniques in designing and realizing wideband digital receivers. Parallel ADCs system is very popular, which sample signals time-interleaved. It provides a way for high speed and high resolution sampling. This dissertation analyzes the mismatches in channels and its influence to ADC system performance, then proposed a way to calibrate the channel imbalances. An experimental ADC system with two AD9430 is developed to demonstrate the proposed method. The dissertation also introduces four high efficient DDC structures suitable for wideband receivers. A way to real timely produce NCO data is proposed and a modified algorithm is introduced for CIC filter. Dynamic range is very important for receivers, so the dissertation investigate the method to improve the range. We discuss several AGC iterative models and their convergence conditions, and then design two practical receivers with big dynamic range. Channelization is another way to realize wideband digital receivers, this dissertation proposed WOLA and tree structures for channelizer. Combine IFM receiver with channelizer provide a method to solve channel fuzzy and low frequency accuracy. Finally, the dissertation designs a general hardware and realizes three different structure and parameters receivers. Their band widths are30MHZ, 50MHz and 100MHz.The novel ideas in this dissertation are as follows:1) Influences of mismatch errors between parallel ADC channels are analyzed in detail. Then we proposed two methods to measure the errors in frequency domain and time domain. Farrow structure is employed to compensate the errors.2) Four efficient DDC structures are proposed for wideband digital receivers, including postpositional mixer, least common multiple structure, double frequency transfer structure and optimum sampling frequency structure. CORDIC algorithm is used to produce NCO data real timely and cosine pre-filtering, non-recursive and sharpening CIC filter is proposed.3) Four iterative AGC models and their convergence conditions are analyzed. Based on the models, we design two practical receivers with AGC.4) The dissertation introduces two efficient structures for channelizers, which are WOLA structure and tree structure and deduces a general structure for polyphase DFT channelizer.5) Two AD9430 are employed to construct a parallel sampling system. The mismatch errors are measured and calibrated in FPGA. The ENOB is 9.26 bit and SFDR is 60dB at 400 sample frequency.6) Three receivers with 30MHz, 50MHz and 100MHz bandwidths are realized on AD 12400 and Xilinx FPGA.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > Receiver equipment, radio Radio > Receiver: the form of points
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