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Research on Electrical Characteristics of Dual-poly Gate Multi-step Field Plate LDMOS

Author: GaoShan
Tutor: ChenJunNing;KeDaoMing
School: Anhui University
Course: Circuits and Systems
Keywords: dual-poly gate multi-step field plate LDMOS RESURF principle
CLC: TN386
Type: PhD thesis
Year: 2007
Downloads: 288
Quote: 3
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Abstract


With the development of power semiconductors and systems integration technology, increasing attention has being paid to power devices. The invention of MOS-controlled power devices has introduced the concept of PICs (Power Integrated Circuits) which can satisfy more rigorous market requirements on reliability, dissipation, cost, size etc. for electronic systems by integrating the power devices and the logic control circuits into a single chip. Among all kinds of novel power devices, LDMOS is attached great importance to the applications of PICs and RF ICs because of its good performances of the breakdown voltage and on-resistance, and easy integration into the standard flow of CMOS process.Since power devices have great effects on volume, weight, cost, efficiency performances and reliability, many new techniques are applied in LDMOS devices to meet market requirements. For the sake of this situation, the structures and processes of LDMOSTs keep improving and the derivative structures of LDMOS structures emerge endlessly, which brings more trouble to device modeling. Unfortunately, once the structures of devices are changed, the device model also needs to be modified. Especially when some new mechanisms come into being in these novel devices, the model must be re-established, otherwise it can not predict the electrical characteristics of devices well and guide the IC design.In this dissertation, a new structure of dual-ploy gate (DPG) multi-steps field plate (MSFP) RESURF LDMOS is proposed based on current technologies of high voltage power devices. The device is superior to the conventional LDMOS in the performance indexes of drive current, breakdown voltage, transconductance, gain, cut-off frequency and its process with a few additional complexities still keeps compatible with standard CMOS process flow. Furthermore, the proposed structure can obviously suppress scaling-down effects and its threshold voltage can be more easily designed.Currently, there are few physical mechanisms for the special structure LDMOS, to say nothing of the electrical characteristics modeling. Therefore, this dissertation establishes some analytical models of the electrical characteristics for DPG MSFP RESURF LDMOS. Then its physical mechanisms are analyzed and optimum design schemes are also given out on the basis of those models. Analytical models independent of test results may predict the electrical characteristics of the proposed device and sppport the theories for circuit simulation model. The electrical characteristics for DPG MSFP RESURF LDMOS are studied here systematically as follows:First, the reasons why dual-poly gates can improve the performances of LDMOS are investigated according to a series of analyses on MEDICI simulation data. The data demonstrate that the step electric potential and the peak electric field which result from the workfunction difference of dual poly gate make differences between the proposed structure and conventional LDMOS. In terms of the conclusion, the functions of surface potential and electric field distribution including the doping concentration density gradient are solved out by 2-D Poisson’ equation. Then the quasi 2-D threshold voltage model of DPG LDMOS is presented which is verified by simulation. The model reflects the effects of the structure parameters (the workfunction difference and the proportion of the length of two gates) on the threshold voltage of DPG LDMOS and can provide theory gists for optimum design of the DPG. In addition, the analytical expression of surface potential can explain how SCEs(Short Channel Effects) and DIBL(Drain Induced Barrier Lowing) is suppressed in DPG LDMOS.Secondly, it is presented that the velocity overshoot produced by the peak of the electric field is the main reason for affecting the current electrical characteristics after analyzing the phenomenon in that the current of the proposed LDMOS is larger than that of conventional LDMOS and the errors which come from the classical model are directly replanted to DPG LDMOS. The extended transport equation combined with the Poisson equation to present an analytical expression of channel current is applied to describe the current characteristics of DPG LDMOS. On the basis of the velocity overshoot model, a simple current model of DPG LDMOS is presented in order to be embedded in circuit simulation softwares easily.Thirdly, although the structure of LDMOS devices is changeable, there exists a RESURF drift region in almost all the LDMOS. Charge sharing theory can well explain how the RESURF principle reduces the breakdown voltage of device and provides a method to build the model of breakdown voltage in the RESURF drift region. However, it is noted that the charge sharing factor is replaced by an experimental parameter in the existing researches because of the absence of a calculation model. In this thesis, the author proposes a model of the charge sharing factor at the corner of drift region in LDMOS based on conformal transformation, and the model is used to compute breakdown voltage in RESURF structure. The results make a good agreement with simulation data.Finally, the use of field plate is a general terminal technology to improve voltage endurance. A multi-step field plate does better in voltage endurance. Consequently, the author present the models of the potential and electric field on the surface of drift region in LDMOS with Double-RESURF technology and multi-steps field plate. Then the length of each step field plate is optimized according to the quasi 2-D derived electric field model. Meanwhile, the relationship between the process and structure parameters of drift region and the breakdown voltage of the device is demonstrated in the model which can support the modeling of breakdown voltage.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Semiconductor technology > Field-effect devices
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