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Application Oriented Research on Deghost in Television Broadcasting

Author: HuangZuoYing
Tutor: HeZuoGang
School: Hunan University
Course: Electrical Engineering
Keywords: Ghost canceller adaptive equalizer Soc DAC ADC PLL
CLC: TN948.13
Type: PhD thesis
Year: 2008
Downloads: 80
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Abstract

Over the past several decades, ghosts are one of the annoying problems in television broadcasting . Ghosts can be seen as echoes or channel dispersion. It has great damage on the quality of communication in analog and digital broadcasting . In recent years, the technique of deghost has been developed . It takes advantage of ghost canceling and equalization.This dissertation focus on the theme about ghost cancellation and adaptive equalization of television broadcasting and follows the basic principles of low voltage, low-power design. A video ghost canceller Soc was developed. In short, the main works of this dissertation are as follows:1. Disclosed is a ghost cancellation system based on an enhanced ghost cancellation reference signal for noisy environments. The received analog television signal is first subjected to a digitization step for processing in the digital domain. A wavelet de-noising operation is applied on the reference signal to remove undesired noises before a communication channel is estimate, and the filter coefficients are optimally determined. The digitized composite signals are the ghost-reduce by IIR and FIR filters. The power consumption and training time of the realized system are decreased, which is ideal for mobile and platform applications.2.The research on equalizer design has been done. In order to solve the problem that the equalizer occupies too much hardware resources, this dissertation proposes tap-decimated equalizer which groups the taps into different sections. Based on this, a digital filter chip was designed. This chip performs the functions required for adapt equalizing and has the cancellation of–6.15μS precursor ghosts through +41.6μS post-cursor ghosts. It was fabricated in a 0.35μm CMOS process and the active area is 5.6 mm2 .3. The research on ghost cancellation Soc design has been done. The Soc can performs all the functions required for ghost cancellation, comprises DSP controllers, memory, syn detection, D/A converters, A/D converters and user programming. The device was encapsulated in 80-pin QFP and the active area (PADs included) is 280mm2 in a 0.35-um CMOS process,operating with 3.3V power supplies and dissipating 1.3W at a rate of 14.318 MHz (4Fsc). Several blocks of this Soc are presented as follows: (1)A 10-bit,150Msamples/s pipelined ADC was presented.The power of the ADC is reduced by using dynamic comparators. The ADC has high dynamic performance when the input frequency is higher than the sampling frequency by using a bootstrap switch in the sample and hold amplifier (SHA). The ADC was fabricated in a 0.35μm CMOS process and the active area is 2.8 mm2 . The measured integral and differential nonlinearity errors of the ADC at the full sampling rate are less than 1.15 LSB and 0.75 LSB, respectively. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 52.4 dB for an input frequency of 80 MHz. The power dissipation is 97 mW.(2)A 10-bit 200-MHz CMOS current steering DAC was presented . The proposed DAC is composed of a unit decoded matrix for 6 MSB’s and a binary weighted array for 4 LSB’s. A new switching scheme for the unit decoded matrix is developed to improve linearity further. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth. The circuit is fabricated in a 0.35μm CMOS process and occupies 0.91 mm2. When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3V power supply.(3)The Input Reference Clock and PLL of the Soc were also described. The PLL was in good performance when the power supply voltage was between 2.5V and 3.3 V, and the temperature was between 0℃and 75℃. The lock times are below 6μs. The clock lock range spans from 10 to 75 MHz.A conclusion and present work are given at the end of the dissertation.

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