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Co-simulation Based RTL Fault Behavior Research

Author: SongJingKai
Tutor: JiChunGuang
School: Harbin Institute of Technology
Course: Computer Science and Technology
Keywords: fault injection co-simulation RTL fault behavior
CLC: TN407
Type: Master's thesis
Year: 2013
Downloads: 3
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Abstract


With the progress of chip manufacturing technology and the adhere to Moore’s lawin chip manufacturing industry, chip size already comes into Nano scale, however, theworking voltage does not decrease compared to the chip, the rise of the working currentdensity and temperature not only lead to transient fault, intermittent fault threaten theprocessor more and more.Simulation based fault injection has good controllability andobservability, but the traditional simulation method can only observe fault behavior atthe hardware level, observation of upward propagation of fault and performance inapplication level is impossible. Software and hardware co-simulation method canovercome this limitation, becomes the mainstream validation method of IC design.We study the co-simulation environment, base on the two simulators ofOpenSPARC open source projects, set up the platform of the fault injection based on theco-simulation and fault analysis, implement injecting fault and observing fault in theregister transfer level simulator, and observe the fault performance and transmission onthe level of microstructure, structure, processor and application, to provide aquantitative evaluation index for the processor reliability.First of all, we analyze the register transfer level simulator and structure levelsimulator in the OpenSPARC combined simulation environment, and study the interactof the simulator in the combined simulation environment, and on this basis complete theconstruction of combined simulation environment which can run the operating system,formulate the application layer communication protocol, and design the capturemechanism of the events of the processor’s memory and trap. We design the faultinjection system under the co-simulation environment, including the fault injector,tracking file collector and statistics analyzer. According to the fault model we carry outthe experiment of fault injection on the target system, statistic the data of experiment.We analyze the sensitivity under various fault models, and the spread characteristic ofthe fault from the bottom to the application layer, and make the suggestions of thedesign of fault-tolerant mechanism.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Testing and inspection
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