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Research and implementation of FPGA SDR digital receiver carrier synchronization system

Author: BaiYuan
Tutor: WangGuoQiang
School: Heilongjiang University
Course: Signal and Information Processing
Keywords: software defined radio digital receiver carrier synchronization costas loop FPGA
CLC: TN851
Type: Master's thesis
Year: 2012
Downloads: 92
Quote: 3
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In recent years, software defined radio (SDR) has been widely recognized for itsmodular, flexibility, scalability, and many other advantages in the field of wirelesscommunications. The core of the SDR is that realizes the different function by loadingdifferent software module in the general hardware platform. The carrier synchronizationwhich is the premise of the communication system to receive information reliably is oneof the key technologies in the SDR receiver. The performance of the carriersynchronization will directly affect the quality of communication. FPGA technologywhich has a very strong programmable ability provides a good platform for SDRreceiver to realize a variety of algorithm. This article has precisely used the FPGAdevelopment platform to study the carrier synchronization system of the SDR receiver.The thesis firstly describes the basic theories of software defined radio in order toprovide the theoretical basis for the design of this article. Then several kind of commoncarrier synchronization algorithm has been researched. Through analyzing andcomparing, the carrier synchronization algorithm has been determined of this system:Costas carrier synchronization. On this basis, the overall design of the system has beendetermined. And the main modules of the carrier synchronization system have beendesigned. Furthmore, the design of the hardware platform has been completed.Afterwards, the carrier synchronization loop has been modeled and simulated on theMATLAB platform. The simulation results have proved the correctness of the structureand the algorithm about the loop. Then according to the design of the hardware platform,the PCB electric circuit board has been manufactured. On the designed hardwareplatform, Verilog HDL code has been written using QuartusII development software torealize the FPGA implementation of SDR transmitter and receiver. And the SignaltapIIonline logic analyzer has been used to finish the hardware simulation and the test for the system.In the design, integral and accumulators have been used to achieve the low-passfiltering instead of the traditional low-pass filter. The higher accuracy of the arctangentalgorithm has been used to detect phase error to replace the traditional multiplicationalgorithm. The higher accuracy of the arctangent algorithm has been used to detectphase error to replace the traditional multiplication algorithm. And the arctangentalgorithm has been realized by the CORDIC algorithm when the design implement onthe FPGA platform. The experimental results show that the design of this carriersynchronization loop is simple, and the speed of convergence and the stability are well.The loop can effectively eliminate the frequency offset and to be able to properly restorethe baseband signal. Thus the correctness and the realizability of the system have beenverified. Therefore, the designed sysyem has a good value of engineering application.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > Receiver equipment, radio Radio > Receiver: the form of points
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