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Research on the RTL Components Design Automation

Author: XuJunPing
Tutor: ChengLiXin
School: Harbin Engineering University
Course: Computer System Architecture
Keywords: RTL components Logic synthesis Layout Simulated Annealing Interconnect delay
CLC: TN602
Type: Master's thesis
Year: 2011
Downloads: 4
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Abstract

Physical parasitics into the deep sub-micron process dimensions of integrated circuits, interconnect delay began to dominate the performance of the integrated circuit design needs to be high-level synthesis and floorplanning combined. In this process can not directly access the static RTL components, mainly because: First, the the static RTL components interconnect delay processing is difficult to meet the needs of the design process; RTL components aspect ratio is fixed, and can not change their shape. Therefore, the combination of high-level synthesis and floorplanning process must be dynamically generated RTL components. This paper studies the RTL components automatically design methods, including the RTL component design three phases: logical function synthesis, physical layout and parameter extraction. First, for a given logic function logic synthesis. QM logic function algorithm based on improved use of new merger rules, and proposed a more efficient, accurate simplification algorithm. Reduced by setting the two weights in the iterative comparison process can be combined implication of the size of the collection and the merge processing only the conditions Implicant meet, get all quality Implicant. The construct quality Implicant minimum Relationships, heuristic rules implication all minterm least of qualitative implication collection of items to obtain minimum coverage of the logic function to complete the simplification of logic functions. Secondly, the use of the simulated annealing algorithm to complete the layout required to implement the logic function module, so that the smallest rectangular envelope all modules in the layout under. Layout based on Slicing structure, indicating that the method using Reverse Polish Notation. In the simulated annealing algorithm, a reasonable choice of relevant parameters, to complete the layout. The preparation of graphics display program, intuitive relative positional relationship of the display module. Finally, the extraction of the RTL components area and delay time parameter. After preorder Slicing Tree, calculating a rectangular area of ??the left and right child nodes of each operation, and eventually get the root area of ??the RTL components area. The delay parameter extraction Elmore interconnect delay calculation formula module connection between the delay time, and then iterate through each input to output transmission path, choose the maximum delay time as RTL components end-to-end delay parameters. The realized three stages of RTL components designed to automatically run time Contrast this topic logic function algorithm with other methods, experimental results show that this topic logic function algorithm simplification faster. In this article, as well as comparing the area of ??utilization of the layout algorithm strategy based on simulated annealing based local search strategy, based on the experimental results, the method in this topic area utilization is high, the algorithm has better robustness. The RTL components automatically design examples are given at the end of this article, the experimental results show that this topic is feasible.

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