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Design of An Embedded CMOS Dynamic Latch Comparator and Whole-chip ESD Protection

Author: XieJing
Tutor: JinXiangLiang
School: Xiangtan University
Course: Microelectronics and Solid State Electronics
Keywords: ASIC embedded dynamic latch comparator whole-chip ESD protectioncircuit
CLC: TN432
Type: Master's thesis
Year: 2013
Downloads: 29
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Abstract


The ASIC readout circuit of low-power MEMS sensor is a chip which processescapacitance signals from sensor, translates the capacitance variation into electrical signalwhich has been decreased noise and amplified. An embedded CMOS dynamic latchcomparator is needed to compare the output signal of5thsigma-delta modulator analogloop with0V reference voltage, and generate digital signals for clock generator block asmode control signal. This work is supported by National Science and TechnologyMajor Project of the Ministry of Science and Technology of China(20112x05008-005-04-02). For the project, the supply voltage of the comparator is5Vand-5V; the clock frequency could be128KHz; the resolution should be lower than5mV with the power consumption is less than1mW.This thesis describes a general introduction on the development of the comparator,and the principle and structures. According to the demand of the project, an embeddedCMOS dynamic latch comparator are designed. Meanwhile, based on the workingprinciple and type choosing the whole-chip ESD protection circuits are proposed andfabricated in this paper.The main work includes that the comparator without offset storage andpreamplification stages circuits which has simple structure, lower consumption andsmall layout area are proposed to improve the performance of traditional structures. Italso uses a set of controlling clock to reduces power consumption, and aswing-minimizing circuit, latch structure to decrease input offset and improve resolution.During the layout design of the embedded CMOS dynamic latch comparator, theinfluence of the match of the differential pair MOSFET and the current source isanalyzed. A cross-quading layout technique is used in the differential pair to match theeffect of parasitic capacitors and resistors. The common centroid layout technique is alsoused in the current source and it is very good at reducing the effect of thermal or processlinear gradients.Meanwhile the input, output and power clamp ESD protection circuits are designed,thus the whole-chip ESD protection network are achieved. During the design of thewhole-chip ESD protection circuit, all kinds of ESD protection devices and structuresare discussed, and designed the whole-chip ESD protection network. In the layout design of ESD protection circuits, the current discharging path of ESD network isanalyzed, the tape-out experience of ESD devices and the optimize layout technique areconsidered for a better ESD performance.The comparator are fabricated in MXIC0.5μm CMOS standard technology, themeasured results show that it has the input offset voltage of9mV, and can distinguisheffectively2.63mV under+/-5V supply voltage at128KHz clock frequency, with only49μW power consumption. The comparator occupies a chip size of130μm×225μm,moreover it can meet the engineering requirements well. The whole-chip ESD protectioncircuits are maken in the same technology.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > Semiconductor integrated circuits ( solid state circuits ) > Field-effect type
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